IEEE VLSI 2017-2018

[vc_row][vc_column width=”1/1″][vc_column_text]VLSI IEEE TRANSACTION – 2017-18

LOW POWER

1 A 2.5-ps Bin Size and 6.7-ps Resolution FPGA Time-to-Digital Converter Based on Delay Wrapping and Averaging
2 Adaptive Multi-bit Crosstalk-Aware Error Control Coding Scheme for On-Chip Communication
3 Coordinate Rotation-Based Low Complexity K-Means Clustering Architecture
4 Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding
5 A Way-Filtering-Based Dynamic Logical–Associative Cache Architecture for Low-Energy Consumption
6 Resource-Efficient SRAM-based Ternary Content Addressable Memory
7 Write-Amount-Aware Management Policies for STT-RAM Caches
8 Fault Diagnosis Schemes for Low-Energy Block Cipher Midori Benchmarked on FPGA
9 High-Throughput and Energy-Efficient Belief Propagation Polar Code Decoder
10 High-Speed Parallel LFSR Architectures Based on Improved State-Space Transformations
11 Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST
12 Stochastic Implementation and Analysis of Dynamical Systems Similar to the Logistic Map

HIGH SPEED DATA TRANSMISSION

13 Efficient Designs of Multi-ported Memory on FPGA
14 High-Speed and Low-Latency ECC Processor Implementation Over GF(2m) on FPGA
15 An On-Chip Monitoring Circuit for Signal-Integrity Analysis of 8-Gb/s Chip-to-Chip Interfaces With Source-Synchronous Clock
16 A 2.4–3.6-GHz Wideband Sub-harmonically Injection-Locked PLL with Adaptive Injection Timing Alignment Technique
17 Hardware-Efficient Built-In Redundancy Analysis for Memory With Various Spares
18 Fast Automatic Frequency Calibrator Using an Adaptive Frequency Search Algorithm
19 A High-Efficiency 6.78-MHz Full Active Rectifier with Adaptive Time Delay Control for Wireless Power Transmission
20 Scalable Device Array for Statistical Characterization of BTI-Related Parameters

AREA EFFICIENT/ TIMING & DELAY REDUCTION

21 VLSI Design of 64bit × 64bit High Performance Multiplier with Redundant Binary Encoding
22 A Method to Design Single Error Correction Codes with Fast Decoding for a Subset of Critical Bits
23 ENFIRE: A Spatio-Temporal Fine-Grained Reconfigurable Hardware
24 Hybrid Hardware/Software Floating-Point Implementations for Optimized Area and Throughput Tradeoffs
25 Efficient Soft Cancelation Decoder Architectures for Polar Codes
26 Low-Complexity Digit-Serial Multiplier Over GF(2m) Based on Efficient Toeplitz Block Toeplitz Matrix–Vector Product Decomposition
27 Hybrid LUT Multiplexer FPGA Logic Architectures
28 Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication
29 FPGA Realization of Low Register Systolic All-One-Polynomial Multipliers over GF (2m) and Their Applications in Trinomial Multipliers
30 Low-Complexity Transformed Encoder Architectures for Quasi-Cyclic Non-binary LDPC Codes Over Subfields
31 Antiwear Leveling Design for SSDs With Hybrid ECC Capability
32 Energy-Efficient VLSI Realization of Binary64 Division with Redundant Number Systems

Audio, Image and Video Processing

33 A Dual-Clock VLSI Design of H.265 Sample Adaptive Offset Estimation for 8k Ultra-HD TV Encoding
34 RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing
35 Energy-Efficient Reduce-and-Rank Using Input-Adaptive Approximations
36 Dual-Quality 4:2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers
37 An FPGA-Based Hardware Accelerator for Traffic Sign Detection
38 Soft Error Rate Reduction of Combinational Circuits Using Gate Sizing in the Presence of Process Variations
39 Time-Encoded Values for Highly Efficient Stochastic Circuits
40 Design of Power and Area Efficient Approximate Multipliers

VERIFICATION

41 COMEDI: Combinatorial Election of Diagnostic Vectors From Detection Test Sets for Logic Circuits
42 Reordering Tests for Efficient Fail Data Collection and Tester Time Reduction

NETWORKING

43 Multicast-Aware High-Performance Wireless Network-on-Chip Architectures

VLSI – BACK END PROJECT – TANNER(nm) / HSPICE(nm) / DSCH3 – MICROWIND(um)

44 Temporarily Fine-Grained Sleep Technique for Near- and Sub-threshold Parallel Architectures
45 Low-Power Design for a Digit-Serial Polynomial Basis Finite Field Multiplier Using Factoring Technique
46 Title: Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator
47 10T SRAM Using Half-VDD Precharge and Row-Wise Dynamically Powered Read Port for Low Switching Power and Ultralow RBL Leakage
48 Delay Analysis for Current Mode Threshold Logic Gate Designs
49 Area and Energy-Efficient Complementary Dual-Modular Redundancy Dynamic Memory for Space Applications
50 Probability-Driven Multi-bit Flip-Flop Integration With Clock Gating
51 A High-Speed and Power-Efficient Voltage Level Shifter for Dual-Supply Applications
52 A 0.1–2-GHz Quadrature Correction Loop for Digital Multiphase Clock Generation Circuits in 130-nm CMOS
53 Conditional-Boosting Flip-Flop for Near-Threshold Voltage Application
54 An All-MOSFET Sub-1-V Voltage Reference With a−51-dB PSR up to 60 MHz
55 A 65-nm CMOS Constant Current Source with Reduced PVT Variation
56 A Fault Tolerance Technique for Combinational Circuits Based on Selective-Transistor Redundancy
57 Temporarily Fine-Grained Sleep Technique for Near- and Sub-threshold Parallel Architectures
58 A 100-mA, 99.11% Current Efficiency, 2-mVppRipple Digitally Controlled LDO with Active Ripple Suppression
59 Sense Amplifier Half-Buffer (SAHB): A Low-Power High-Performance Asynchronous Logic QDI Cell Template
60 On Micro-architectural Mechanisms for Cache Wear out Reduction
61 Energy-Efficient TCAM Search Engine Design Using Priority-Decision in Memory Technology
62 A 92-dB DR, 24.3-mW, 1.25-MHz BW Sigma–Delta Modulator Using Dynamically Biased Op Amp Sharing
63 A 0.45 V 147–375 nW ECG Compression Processor With Wavelet Shrinkage and Adaptive Temporal Decimation Architectures

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