Analysis and Design of a Low-Voltage Low-PowerDouble-Tail Comparator
Abstract:
The need for ultralow-power, area efficient and high speed analog-to-digital converters is pushing toward the use of dynamic regenerative comparators to maximize speed and power efficiency. In this paper, an analysis on the delay of the dynamic comparators will be presented and analytical expressions are derived. From the analytical expressions, designers can obtain an intuition about the main contributors to the comparator delay and fully explore the tradeoffs in dynamic comparator design. Based on the presented analysis, a new dynamic comparator is proposed, where the circuit of a conventional double-tail comparator is modified for low-power and fast operation even in small supply voltages. Without complicating the design and by adding few transistors, the positive feedback during the regeneration is strengthened, which results in remarkably reduced delay time. Postlayout simulation results in a 0.18-µm CMOS technology confirm the analysis results. It is shown that in the proposed dynamic comparator both the power consumption and delay time are significantly reduced. The proposed architecture of this paper is analysis the logic size, area and power consumption using tanner tool.
Enhancement of the project:
We are implementing the comparator in sigma delta modulator design.
Existing System:
Clockedregenerativecomparatorshavefoundwideapplicationsinmanyhigh-speedADCssincetheycanmakefast decisionsduetothestrongpositivefeedbackinthe regenerativelatch.
Conventional Dynamic Comparator:
TheschematicdiagramoftheconventionaldynamiccomparatorwidelyusedinA/Dconverters,withhighinput impedance,rail-to-railoutputswing,andnostaticpower consumptionis shown in Fig. 1.The operationofthe comparator is as follows. During the reset phase when CLK =0 and Mtailis off, reset transistors (M7–M8) pull both output nodes Outn and Outpto VDDto define a start condition and to have a validlogicallevelduringreset.Inthecomparisonphase,when CLK =VDD,transistors M7and M8areoff,and Mtailison. Outputvoltages(Out p,Outn),whichhadbeenpre-chargedto VDD,starttodischargewithdifferentdischargingrates dependingonthecorrespondinginputvolt-age(INN/INP). Assuming the case where VINP>VINN, Outpdischarges faster than Outn, hence when Out p(discharged by transistor M2drain current),fallsdownto VDD–|Vthp| beforeOutn(dischargedby transistor M1draincurrent), the corresponding pMOS transistor (M5) will turn on initiating the latch regeneration caused by backto-back inverters (M3, M5and M4, M6). Thus, Outn pulls to VDD and Outpdischarges to ground. If VINP<VINN, the circuits works vice versa.
Figure 1: Schematic diagram of the conventional dynamic comparator
Conventional Double-Tail Dynamic Comparator:
A conventional double-tail comparator is shown in Fig. 2. This topology has less stacking and therefore can operate at lower supply voltages compared to the conventional dynamic comparator. The double tail enables both a large current in the latching stage and wider Mtail2, for fast latching independent of the input common-mode voltage (Vcm), and a small current in the input stage (small Mtail1), for low offset. The operation of this comparator is as follows (see Fig. 4). During reset phase (CLK =0, Mtail1, and Mtail2 are off), transistors M3-M4pre-charge fn and fp nodes to VDD, which in turn causes transistors MR1and MR2to discharge the output nodes to ground. During decision-making phase (CLK =VDD, Mtail1 andMtail2turn on), M3-M4turn off and voltages at nodes fn and fp start to drop with the rate defined by IMtail1/Cfn (p) and on top of this, an input-dependent differential voltage Vfn(p) will build up. The intermediate stage formed by MR1and MR2passes Vfn(p) to the cross coupled inverters and also provides a good shielding between input and output, resulting in reduced value of kickback noise.
Figure 2: Schematicdiagramoftheconventionaldouble-taildynamiccomparator
Disadvantages:
- Power consumption is high
Proposed System:
A comprehensive analysis about the delay ofdynamic comparators has been presented for various architectures. Furthermore, based on the double-tail structure proposed, anew dynamic comparatoris presented,which does notrequireboostedvoltageorstackingoftoomany transistors. Merely by adding a few minimum-size transistors totheconventionaldouble-taildynamiccomparator,latch delaytimeisprofoundlyreduced.This modification also results in considerable power savings when compared to the conventional dynamic comparator and double-tail comparator.
Fig. 3 demonstrates the schematicdiagramoftheproposeddynamic double-tail comparator. Due to the better performance of double-tail architecture in low-voltage applications, the proposed comparator is designed based on the double-tail structure.The main idea of the proposed comparator is to increase Vfn/fpin order to increase the latch regeneration speed.For thispurpose,twocontroltransistors(Mc1and Mc2)havebeenaddedtothefirst stage in parallel toM3/M4transistors but in a cross-coupledmanner.
Figure 3: Schematic diagram of the proposed dynamic comparator. (a) Main idea. (b) Final structure
The CT ∑-∆ ADC is shown in Fig. 4. It is composed of three RC integrators, in addition to, a summing amplifier, a single-bit comparator, and an RZ DAC. The three active RC integrators are designed to build the ∑-∆ loop filters, using the proposed tunable inverter-based OTA. The first integrator is allocated most of the noise budget. The outputs of the three integrators are summed together by the summing amplifier, built using the same tunable inverter-based OTA topology. The OTAs of the other two integrators and the summing amplifier are the scaled versions of the first integrator OTA. All loop filters coefficients are scaled to obtain a reasonable signal swing at the integrators outputs and the comparator input
Figure 4: Implemented ∑-∆ modulator
The feedback RZ DAC is shown in Fig. 5. It is a differential push–pull current steering DAC. Logic gates, shown in Fig. 6, are designed to control switches (M1–M4), such that RZ pulse shaping is obtained. M5 and M6 are used to keep current sources working continuously while switching to maintain robust operation.
Figure 6: Logic gates of the RZ DAC.
A standard CMOS inverter can be operated as a voltage amplifier if both the nMOS and pMOS transistors constituting the inverter are kept in the saturation region. This results in high transconductance and output resistance, and consequently high dc gain and GBW. Fig. 7 shows the structure of the proposed tunable inverter-based low-voltage amplifier.
Figure 7: Tunable inverter-based OTA
The tuning technique is basically a CM feedback (CMFB) circuit that senses the output CM voltage and controls the current flow through the inverter using four controlled current sources. Fig. 8 shows the tuning circuit implementation. The CM of the OTA is extracted using two resistors and compared with a reference voltage (Vref), set at the half the supply voltage, using an amplifier, Acm. The output of the amplifier controls the nMOS and pMOS current sources (MI1–MI4). The CMFB current sources can source or sink current into the main OTA. The Acm amplifier is a simple pseudo differential amplifier, as shown in Fig. 9. At a certain temperature and process corner, if the output CM voltage (Vcmout) is lower than Vref, then Vctrl becomes low. This forces MI3 and MI4 transistors to source more current into the main OTA until Vcmout nearly equals Vref. The opposite operation happens when Vcmout is higher than Vref.
Advantages:
- Reduce the power consumption
Software implementation:
- Tanner EDA