Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST
Abstract:
The generation of significant power droop (PD) during at-speed test performed by Logic Built-In Self Test (LBIST) is a serious concern for modern ICs. In fact, the PD originated during test may delay signal transitions of the circuit under test (CUT): an effect that may be erroneously recognized as delay faults, with consequent erroneous generation of test fails and increase in yield loss. In this paper, we propose a novel scalable approach to reduce the PD during at-speed test of sequential circuits with scan-based LBIST using the launch-on capture scheme. This is achieved by reducing the activity factor of the CUT, by proper modification of the test vectors generated by the LBIST of sequential ICs. Our scalable solution allows us to reduce PD to a value similar to that occurring during the CUT in field operation, without increasing the number of test vectors required to achieve target fault coverage (FC). We present a hardware implementation of our approach that requires limited area overhead. Finally, we show that, compared with recent alternative solutions providing a similar PD reduction, our approach enables a significant reduction of the number of test vectors (by more than 50%), thus the test time, to achieve a target FC. The proposed architecture of this paper analysis the logic size, area and power consumption using Xilinx 14.2.
Existing System:
At-speed test of logic blocks is nowadays frequently performed using Logic BIST (LBIST), which can take the form of either combinational LBIST or scan-based LBIST, depending on whether the CUT is a combinational circuit or a sequential one with scan. In case of scan-based LBIST, two basic capture-clocking schemes exist: 1) the launch-on-shift (LOS) scheme and 2) the launch-on-capture (LOC) scheme. In LOS schemes, test vectors are applied to the CUT at the last clock (CK) of the shift phase, and the CUT response is sampled on the scan chains at the following capture CK. In the LOC scheme, instead, test vectors are first loaded into the scan-chains during the shift phase; then, in a following capture phase, they are first applied to the CUT at a launch CK, and the CUT response is captured on the scan chains in a following capture CK. In this paper, we consider the case of sequential CUTs with scan-based LBIST adopting an LOC scheme, which is frequently adopted for high-performance microprocessors. They suffer from the PD problems discussed above, especially during the capture phase, due to the high AF of the CUT induced by the applied test patterns.
We consider the conventional scan-based LBIST (Conv LBIST) architecture shown in Fig. 1. The state flip-flops (FFs) of the CUT are scan FFs, arranged into many scan chains (s scan chains in Fig. 1). The pseudorandom pattern generator is implemented by an LFSR. The PS, which reduces the correlation a the test vectors applied to adjacent scan-chains, is composed of an XOR network expanding the number of outputs of the LFSR to match the number of scan chainss. The PS gives to its output the current LFSR output configuration, together with future/past configurations at each shift CK.
Figure 1: Schematic of the considered scan-based LBIST architecture.
The Space Compactor compacts the outputs of thes scan chains to match the number of inputs of the Multiple-Input Signature Register (MISR). The MISR, the test response analyzer, and the BIST Controller are the same as in combinational scan-based LBIST.
As for the scan FFs, our approach requires that, during shift phases, they maintain the last test vector applied to the CUT at their outputs. This is guaranteed by the scan-FF, which is frequently employed in microprocessors, and considered here as a significant example. However, this can also be achieved with other different scan FFs. The internal structure of this FF is shown in Fig. 2. It consists of two subblocks, namely, the scan portion and the system portion, each consisting of a master-slave FF composed of two latches (Latches LA and LB for the scan portion, and latches PH2 and PH1 for the system portion). The latches have two clocks, and sample one out of two input data lines, depending on which clock is active.
Figure 2: Considered scan FF and signals’ timing
The clocking scheme adopted to implement an LOC strategy is also reported in Fig. 2. It consists of a shift phase [scan enable (SE=1)] and a capture phase (SE=0). During the shift phase, a new test vector is loaded in the scan chains after n shift CKs, where n is the number of scan FFs of the longest scan chain. At each shift CK, a new bit of the test vector present at the scan_in of latch LA is shifted to the scan_out of latch LB.
Disadvantages:
- Performance is low
Proposed System:
We propose a novel, scalable approach to reduce PD during capture phases of scan-based LBIST, thus reducing the probability to generate false test fails during test. Similar to the solutions, our approach reduces the AF of the CUT compared with conventional scan-based LBIST, by properly modifying the test vectors generated by the Linear Feedback Shift Register (LFSR). Our approach is somehow similar to reseeding techniques, to the extent that the sequence of test vectors is properly modified in order to fulfill a given requirement that, however, is not to increase FC (as it is usually the case for reseeding), but to reduce PD.
Proposed scalable approach:
As we introduced in Section I, the goal of our approach is to reduce the PD that may generate false test fails during at speed test with scan-based LBIST. Such a PD occurs after the application of a new test vector to the CUT. This occurs at the launch CK (Update pulse in Fig. 2) within capture phases. The generated PD is proportional to the CUT AF induced by the application of a new test vector, which in turn depends on the AF of the scan FFs’ outputs [8]. For the considered scan FFs (Fig. 2), such an AF depends on the number of FFs’ outputs switching when the new test vector is applied. Therefore, the target of our approach is to reduce the number of FFs’ outputs transitions occurring after the application of a new test vector to the CUT.
Approach With 1 Substitute Test Vector:
For each scan chainm(m=1…s), one ST vector STmi replaces the original test vector Tmi to be applied to the CUT at the ith capture phase according to Conv-LBIST (Fig. 3). It will be shown that this enables a 50% AF reduction compared with Conv-LBIST. In our approach, the ST vector STmi to be charged in the Scan-Chain (SC)mand applied to the CUT at the ith capture phase is constructed based on the structure of test vectors Tmi−1 and Tmi+1 to be applied at the (i−1)th and (i+1) th capture phases. Assuming the presence of a generic PS, our solution exploits the fact that, during the shift phase preceding the ith capture phase, test vectors T mi−1 and Tmi+1 are given at proper outputs of the PS. Should some test vectors not be produced at the PS outputs, the PS could be easily modified to generate them.
Figure 3: Schematic of (a) sequence of test vectors filling each scan chainm,(b) bits in the ST vector STmi and in the test vectors applied/to be applied at the previous/following capture phase
Advantages:
- Better performance
Software implementation:
- Modelsim
- Xilinx ISE