COMEDI: Combinatorial Election of Diagnostic Vectors From Detection Test Sets for Logic Circuits

**Abstract:**

Although the modern automatic test pattern generation (ATPG) tools can efficiently produce near-optimal test sets with high fault-coverage for a circuit-under-test, a diagnostic test set (DTS), which is needed for fault localization, is much more challenging to construct. The DTS is used to analyze the responses of failing chips during manufacturing test for the purpose of identifying the root cause of observed errors. In this paper, a novel technique for selecting a powerful DTS for stuck-at faults from a pool of ATPG detection vectors is proposed. Unlike existing methods, this technique does not use any diagnostic test generation, circuit modification, or miter-based approach. It constructs a combinatorial cover of the pool to determine a test set with high diagnostic coverage (DC). Two variants of the covering algorithm are proposed based on this technique. The experimental results on several combinational and scan-based benchmark circuits demonstrate the effectiveness of our method in terms of the size of the DTS, DC, and CPU time. The proposed architecture of this paper analysis the logic size, area and power consumption using Xilinx 14.2.

**Existing System:**

All related prior works aim at generating additional vectors so as to improve the DC that is achieved by the detection test set. Gruning et al.proposed a tool for diagnostic test pattern generation (DTPG) based on a branch-and-bound technique for circuit traversal. A miter-based technique to generate distinguishing test vectors using two copies of the circuit was proposed. Based on the observation that the faults in the same fan-out free region are harder to distinguish than the faults being in different fan-out free regions, a method for DTPG is proposed. A miterbased circuit is considered for test pattern generation and a module “SA1” is used to inject a pair of faults into the circuit such that the fault pair is injected if the selection line of the model is set at 1. Unlike, which uses two copies of a circuit for generating a test, the method proposed shows that a similar result can be obtained using only a single circuit. This technique is used to generate exclusive tests for faults, if any, by inserting two multiplexers per fault pair. It proposes a simple diagnostic metric and also discusses a method called dictionary-based fault diagnosis. The work presented provides an improved result using one exclusive test to distinguish many pairs of faults when they have nonintersecting output cones. A DTPG tool based on ault pair collapsing is proposed. It relies on a certain kind of structural analysis of the circuit and diagnostic test sets are generated using a method of test elimination. A SAT-based technique to generate a test set with high diagnostic power is also reported.

Efficient fault collapsing makes DTPG more effective. Previous efforts in this direction include collapsing of equivalent faults, identification of fault pairs that are guaranteed to be distinguished by the fault detection test set, or fault pair collapsing.

**Disadvantages**:

- Accuracy is high

**Proposed System:**

We now formulate the combinatorial problem for determining a diagnostic test cover assuming the stuck-at fault model. Our approach is based on the following observations.

Observation 1: The detection test set of a circuit obtained by ATPG tools for a particular fault model is, in general, quite diverse in nature.

Note that for a given fault, there may exist a number of vectors that can detect the fault and this fact is true for most of the faults, except the hard-to-detect faults. An ATPG tool experiences various options while selecting the smallest detection test set. Different test sets produced by an ATPG tool may provide the same fault coverage. Table III shows the result, where five test sets have been generated using two ATPG tools: ATALANTA [12] and Synopsys TetraMAX [13] for a few ISCAS’85 [29] and ISCAS’89 [30] circuits. By setting an initial random seed, it is possible to generate different test sets in ATALANTA. In Tetra MAX, we can obtain different test sets by randomly filling the “don’t cares” in each pattern. In order to demonstrate this variability, we have generated five different test sets. Let T denote the set of these five sets: T={T1,T2,T3,T4,T5}. For each test set Ti ∈T, we define Ci =Ti∩∼{U^{5}_{j=1}Tj| j = i}, which denotes the set of test vectors that are exclusive in Ti, i.e., they are included in Ti but not in the union of the remaining other test sets. Each entry in Table III shows the value of |Ti |/|Ci |. Note that except for the small circuits c17 and s27, each of the test sets, thus generated, comprises mostly exclusive vectors.

Observation 2: The union of two test sets is likely to increase DC.

A test set containing a larger number of vectors is likely to have a higher DC than the one with fewer vectors. For two different test sets having the same DC, their union often leads to an increase in DC, whenever they have different TE classes, i.e., when they distinguish different sets of faults. This is demonstrated in the motivational example discussed earlier.

Observation 3:If two faults in a circuit that are detected independently (one at a time) by a test vector produce different output vectors, they are distinguishable.

This observation leads to a combinatorial formulation of the diagnosis problem. A distinguishing test vector ought to produce two different output responses for two faults. The TE-classes for a test vector can be computed by comparing fault simulation outcomes. The response vector (R) for a fault is an m-bit binary string, where m denotes the number of circuit outputs (primary and scan outputs for sequential circuits). The output bits of Rare set to 1 where the error is observed. Thus, if the response vectors of a test pattern are different for two faults, they are distinguishable. In our experiment, the primary output pins are considered in a fixed sequence such that the corresponding binary string consisting of observed values can be fairly compared. For scan-based circuits, the flip-flop states, after each test cycle, are also observed similarly, following the primary output pins. Thus, the output vector reflects a fixed sequence of response bits that appears at the primary and secondary outputs.

Data Structure: Response Matrix:

or large circuits, especially for scan-based circuits, the value ofmis large. Instead of comparing two large binary strings for checking distinguishability of two faults, we may consider the unsigned integer of these binary strings. Hence, instead of constructing a 3-D (|F|×|T|×m)binary response matrix, we consider an|F|×|T| 2-D integer response matrix, where Fis a set of detectable structurally collapsed faults and Tis a set of test vectors. However, this would entail a new problem of memory overflow. Typically, a large benchmark circuit may have more than thousand outputs. The unsigned integer representation of such large binary stings would be very large. In order to tackle this problem, we propose a method called matrix relabeling. Note that in order to check whether a test vector distinguishes two faults, their output vectors/integer values should be different; their actual magnitudes are of no significance. Therefore, for each test vector, the output integer values for all faults can be relabeled with smaller values preserving their distinguishability. In other words, each entry in a column of the 2-D response matrix can be relabeled with smaller values (see Fig. 1).

Figure 1: Example of matrix relabeling for s27 circuit.

**Advantages:**

- Accuracy is low

**Software implementation:**

- Modelsim
- Xilinx ISE