Delay Analysis for Current Mode Threshold Logic Gate Designs
Abstract:
Current mode is a popular CMOS-based implementation of threshold logic functions, where the gate delay depends on the sensor size. This paper presents a new implementation of current mode threshold functions for improved gate delay and switching energy. An analytical method is also proposed in order to identify quickly the sensor size that minimizes the gate delay. Simulation results on different gates implemented using the optimum sensor size indicate that the proposed current mode implementation method outperforms consistently the existing implementations in delay as well as switching energy. The proposed architecture of this paper analysis the logic size, area and power consumption using Tanner tool.
Existing System:
two current mode designs (called CMTLG) and (called DCML). The block diagram of the CMTLG is shown in Fig. 1. It consists of the differential part and the sensor part. The differential part is subdivided into two parts: the threshold part and the (positive) inputs part. The inputs part has pMOS transistors that implement the positive input weights. The threshold part has pMOS transistors that implement the threshold weight and the negative input weights. Typically, a weight of value x is implemented by connecting x minimum size pMOS transistors in parallel. (Alternatively, it can be implemented by a single pMOS transistor whose width isx times the minimum size.) In both the parts, all the pMOS transistors are connected in parallel. The total current flowing through the threshold part is denoted by IT. The total current passing through the inputs part is denoted by IA. For each applied input pattern, pMOS active (ON) transistors correspond to input weights for inputs that are assigned a logic value 1. The pMOS transistors that implement the threshold weight are always active (ON).
Figure 1: Current mode TLG
The nodes connecting the differential part and the sensor part on the input side and the threshold side areM1 andM2, respectively. The sensor part has three pMOS transistors P1, P2, P3, and four nMOS transistors N1, N2, N3,andN4 as shown in Fig. 1. If the size of the sensor is S, then all the pMOS transistors in the sensor part have S μm size and all the nMOS transistors in the sensor part have a size smaller than S μm.
Figure 2: Output voltages and their difference in the two clock phases for CMTLG
The operation of the CMTLG is divided into two phases: the equalization phase and the evaluation phase. These phases are explained with the help of Figs. 1 and 2. When the applied clock (clk)to the CMTLG is high, then the circuit is in the equalization phase. When clk is low, then the circuit is in the evaluation phase. In the equalization phase, transistors N1andN2areON, nodes M1andM2have the same voltage because of transistorN1, and nodes O and OB have the same voltage because of transistor N2 (see also Fig. 1). In the evaluation phase, transistors N1 and N2 are OFF, and if the threshold current is less than the active current, then the voltage at node O rises faster than that at node OB. If during the evaluation phase the threshold current exceeds the active current, then the voltage at node OB rises faster than that at node O.
Disadvantages:
- Delay is high
- Energy consumption is high
Proposed System:
A new TLG implementation is proposed. It is called DCCML. As the name indicates, two clocks are used to achieve low power consumption and high speed.
The block diagram DCCML is shown in Fig. 3. As in previous approaches, the DCCML is divided into two basic blocks: the differential block and the sensor block. The differential block is further divided into four blocks: the positive threshold, the negative inputs, the negative threshold, and the positive inputs. All the transistors in the differential block are equal-sized pMOS transistors and are connected in parallel, as shown in Fig. 3. The sensor block consists of six pMOS transistorsP1···P6 and three nMOS transistors N1, N2,andN3. The gates of transistors P1andN1are connected to Clk1 and the gates of transistors P2, P5, and P6 are connected to Clk2. Transistor N1 acts as an equalizing transistor and it equalizes the voltage at nodes OP and OPB. TransistorsP5 and P6 isolate the differential block from the sensor block.
Figure 3: Block diagram of DCCML TLG
The operation is divided into three phases: the equalization phase, the pre-evaluation phase, and the final-evaluation phase. When clocksClk1 andClk2 are high, then the circuit is in the equalization phase. When clocks Clk1 andClk2 are low, then the circuit is in the pre-evaluation phase. When Clk1 is low and Clk2is high, then the circuit is in the final-evaluation phase. See also Fig. 4. It is noted that when the two clocks are not completely aligned the operation of the gate is not effected. The possible cases of misalignment are: 1) the falling edge ofClk2 comes before the falling edge ofClk1 and 2) the falling edge of Clk2 comes after the falling edge ofClk1. In the first case, the current from the differential part is equalized because of transistor N1 and the evaluation phase starts after the falling edge ofClk1. In the second case, there will be no current from the differential part asClk2is not active yet. Hence, the pre-evaluation phase starts after the falling edge ofClk2.The implementation avoids a very early arrival of Clk1.Inthat case, a non-stable signal might result in erroneous output.
Figure 4: Clocks in DCCML
Advantages:
- Delay is low
- Energy consumption is low
Software implementation:
- Tanner tool