A 0.1–2-GHz Quadrature Correction Loop for Digital Multiphase Clock Generation Circuits in 130-nm CMOS

**Abstract:**

A 100-MHz–2-GHz closed-loop analog in-phase/quadrature correction circuit for digital clocks is presented. The proposed circuit consists of a phase-locked loop- type architecture for quadrature error correction. The circuit corrects the phase error to within a 1.5° up to 1GHz and to within 3° at 2GHz. It consumes 5.4 mA from a 1.2 V supply at 2 GHz. The circuit was designed in UMC 0.13-µm mixed-mode CMOS with an active area of 102µm×95µm. The impact of duty cycle distortion has been analyzed. High-frequency quadrature measurement related issues have been discussed. The proposed circuit was used in two different applications for which the functionality has been verified. The proposed architecture of this paper analysis the logic size, area and power consumption using Tanner tool.

**Existing System:**

Quadrature mismatch in wireless transmitters results in poor error vector magnitude performance. In receivers, quadrature imbalance leads to increased bit error rate. In complex transmitters and receivers, the circuits rely on quadrature separation in the clocks to achieve good image rejection. Quadrature errors in these systems directly degrade the image rejection ratio. In wireline communication, quadrature errors worsen the jitter and affect eye parameters. Multiphase clock synthesizers generate fine phase separations by mixing an appropriately weighted pair of clocks that are in quadrature. Hence, quadrature impairments in these circuits affect the performance drastically.

Various quadrature gain and phase correction mechanisms are presented. A BiCMOS implementation of a level-locked loop proposed corrects the error between two quadrature signals from 40–500 MHz by using a bias generated by the loop to shift the dc level of the input clock. Quadrature correction at 4 GHz is achieved by adjusting switched capacitor loads, programmed by a finite state machine, which is controlled by a feedback loop. In-phase/quadrature (IQ) mismatch calibrator circuit presented employs an ultra-wideband phase interpolator to correct the quadrature phase mismatch. The technique works well for multigigahertz frequencies as demonstrated. However, in order to employ them for quadrature correction at lower frequencies, larger time delays need to be generated. This can be done using high threshold devices or IO devices. Some receivers use the baseband techniques for the correction of quadrature mismatches, as presented, the IQ gain and phase mismatch are corrected for in the down conversion mixer by means of variable resistors. An IQ calibration sequence for RF BIST is proposed by on-chip measurements of key performance parameters.

**Disadvantages**:

- Performance is low

**Proposed System:**

We present an analog circuit that can continuously correct quadrature mismatches in RF clocks over a wide frequency range. This was targeted for software defined radio (SDR) and cognitive radio (CR) applications. SDRs span a wide frequency range and the correction circuit needs to work across the entire range. The challenge at a lower frequency is to provide phase shifts which correspond to larger time delays. At high frequencies, the accuracy of correction is important. A fully digital implementation is limited by the technology at these frequencies. Both challenges are addressed in the presented method. An analog delay cell is used to address the problem of accuracy at high frequencies. A cascade of the delay cells increases the absolute time delay that can be corrected, thus solving the range problem at lower frequencies. The proposed technique can also be used as a stand-alone design for wireline and wireless transceivers.

Architecture:

An analog negative feedback loop is used to correct the quadrature error between two clock phases. Direct on-chip sensing of quadrature error for high-frequency clocks is a challenge. In this approach, the quadrature error is converted into a duty cycle error, which can be measured easily on-chip. When two clocks having a duty cycle of 50%, which are in exact quadrature, areXORed, the resulting signal is at twice the clock frequency and has a duty cycle of 50%. A quadrature error between these clocks leads to non-50% duty cycle at the output of theXOR. Fig. 1(a) and (b) demonstrates this concept. This deviation of the duty cycle from 50% is linearly related to the quadrature mismatch between the two clock phases.

Figure 1: Quadrature error leading to duty cycle error. (a)XOR-based doubler output when clocks are in perfect quadrature. (b)XOR-based doubler output in the presence of quadrature errors.

Fig. 2 shows the block diagram of the quadrature error correction loop. A fixed delay is introduced in the I path and a variable delay is introduced in the Q path which is generated by the loop. The fixed delay allows the loop to work over a larger range, as it reduces the relative phase separation between the I and Q phases before correction. Quadrature sensing is done by determining the duty cycle at the output of the XOR. Quadrature correction is obtained by varying the delay in the Q path, such that the duty cycle of the XOR output is corrected to 50%.

Figure 2: Architecture of the quadrature correction loop.

The duty cycle detector (DCD) provides an output voltage, which is proportional to the duty cycle at its input. An operational trans conductance amplifier (OTA) is used to provide gain in the loop and also to generate the control voltage for the variable delay cell. A bias-translation circuit translates the control voltage (VCTRL) to complementary biases for the pMOS (VCTRL_P) and nMOS (VCTRL_N) transistors in the variable delay cell. When the phase separation between the I and Q waveforms is less than π/2, the control loop produces a VCTRL, such that the Q clock has more delay than the fixed delay in the I path. On the other hand, when the phase separation is greater thanπ/2,VCTRL produces a smaller delay than the fixed delay in the I path.

Circuit-level description:

Variable Delay Cell:

The delay cell used in the proposed quadrature correction loop is shown in Fig. 3. The delay cell is a buffer with a current starved inverter followed by a digital inverter to restore the signal polarity and swing. The current-starved inverter consists of a Maneatis load for both nMOS and pMOS.

Figure 3: Delay cell used in thequadrature correction loop.

XOR Cell:

The XOR logic is used to translate the quadrature error to an equivalent duty cycle error. It provides an output at twice the input frequency. For high-frequency input clocks, it is not possible to implement the XOR logic using the standard circuits in a 130-nm CMOS process. Hence, a Current Mode Logic (CML)-based design is used. The implementation has nMOS transistors to evaluate the logic with a pMOS load, as shown in Fig. 4. The circuit is biased at 100μA. The output of the XOR is not rail-to-rail. The ratio of the time duration for which the signal is greater than the common mode voltage to the total time period is taken as the duty cycle.

Figure 4: Schematic of CML-based XOR.

Duty Cycle Detector:

The DCD is a differential amplifier (DA), where the current is steered through one arm or the other by the output of the CML XOR gate. The output node has a large capacitor of 5 pF on each differential arm. The circuit is shown in Fig. 5. It is an active low-pass filter, which generates the differential dc average of the output of the XOR. The dc average is directly proportional to the duty cycle.

Figure 5: DCD

OTA:

The primary function of the OTA is to provide gain in the loop. It generates the control voltage (VCTRL). The circuit is showninFig.6.Itisbiasedat100μA. A telescopic pMOS load is used to boost the gain. A 5-pF capacitor is placed at the output to provide more filtering for the control voltage. The OTA has a gain of 40 dB and its dominant pole is at 150 kHz.

Figure 6: Schematic of OTA

Bias-Translational Circuit:

The two control voltages for the delay cell shown in Fig. 3 are generated from the bias-translational circuit shown in Fig. 7. The circuit takes the output of the OTA, which is proportional to the quadrature error and translatesit to an appropriate value for the nMOS and pMOS control voltages.

Figure 7: Bias-translational circuit

**Advantages:**

- Better performance

**Software implementation:**

- Tanner tool