Hardware-Efficient Built-In Redundancy Analysis for Memory with Various Spares
Abstract:
Memory capacity continues to increase, and many semiconductor manufacturing companies are trying to stack memory dice for larger memory capacities. Therefore, built-in redundancy analysis (BIRA) is of utmost importance because the probability of fault occurrence increases with a larger memory capacity. A traditional spare structure that consists of simple rows and columns is somewhat inadequate for multiple memory blocks BIRA because the hardware overhead and spare allocation efficiency are degraded. The proposed BIRA uses various types of spares and can achieve a higher yield than a simple row and column spare structure. Herein, we propose a BIRA that can achieve an optimal repair rate using various spare types. The proposed analyzer can exhaustively search not only row and column spare types but also global and local spare types. In addition, this paper proposes a fault-storing content-addressable memory (CAM) structure. The proposed CAM is small and collects faults efficiently. The experimental results show a high repair rate with a small hardware overhead and a short analysis time. The proposed architecture of this paper analysis the logic size, area and power consumption using Xilinx 14.2.
Existing System:
In 3-D memories, each stacked die needs a test port to test itself. Using automatic test equipment (ATE) for semiconductor testing, the number of I/O ports increases between the base layer and the ATE. Increasing the number of I/O ports not only causes an increase in the production risk of failure on through silicon-vias (TSV) but also increases the production cost. For the abovementioned reasons, BIRA has been under research for a long time; however, there is an NP-complete problem of allocating row and column spares. Researches on BIRA have attempted to minimize the redundancy analysis (RA) time, hardware overhead, and the repair rate because these features influence the cost and productivity of semiconductors. There are tradeoffs a these features in general. As the memory repair becomes more important, many researches have been performed extensively. 2-D spare structures consist of a simple row and column spare structure. However, these are not limited to achieve a higher yield. In general, a memory consists of several memory blocks or memory banks. In practice, 2-D spares are located for each memory block. Directly applicable for application of this research to practical memories is difficult because most practical memories adopt divided bitline or divided wordline structures to reduce the operational voltage and increase the analysis time by minimizing the operational memory area. Because of the changing operation of the memory, the spare structure has also changed in various ways. Some BIRA researches have covered the various spares; however, this research uses heuristic RA and considers a different spare structure with a traditional row and column spare structure, decreasing the overall yield of the tested memory. To maximize the yield, BIRA of the spare structure with various spares can repair every case of reparable faulty memory using the given redundancies. To obtain an optimal repair rate, an exhaustive search is unavoidable because of the NP-complete problem of allocating row and column spares.
1) Exhaustive Searching BIRA: These are tree-based search BIRAs, which are typically referred to as CRESTA and Fault Driven. CRESTA is a parallel BIRA; it concurrently collects faults and repairs, while also achieving an optimal repair rate. The hardware for CRESTA exponentially increases with an increase in the number of spares, because CRESTA stores every repair case. CRESTA can achieve an optimal repair rate without RA time because it considers every repair case. Despite the hardware overhead, CRESTA has many positive aspects in terms of analysis time and repair rate. To reduce the hardware of CRESTA, R-CRESTA that removes fault address overlap has been proposed, however, the hardware remains too large.
2) Heuristic BIRA: While exhaustive searching-based BIRA algorithms can achieve an optimal repair rate, heuristic BIRA algorithms ESP and LRM cannot achieve an optimal repair rate. This is because, as mentioned above, BIRA with a 2-D spare structure has an NP-complete problem. ESP is a representative heuristic BIRA algorithm. The hardware overhead of ESP is quite small and has a very simple RA method. ESP uses the concept of the pivot fault for the first time; it also uses CAM. When the newly found fault is not shared with a previously stored fault, it is stored on CAM; otherwise, the newly found fault is shared with a previously stored fault, and the sharing address of the previously stored fault is covered by a spare. Unlike ESP, LRM has a 2-D faulty map. It uses a 2-D faulty map as much as the defined faulty map size by the user. The 2-D faulty map requires more storage than the 1-D fault-saving CAM of ESP. Therefore, the hardware of LRM is quite large, and the repair rate can be changed according to the faulty map size defined by the user.
Disadvantages:
- Area coverage is high
Proposed System:
The novelties of the proposed approach are as follows. To obtain a higher repair rate, the proposed BIRA uses various spares such as common spares, local spares, and global spares, as shown in Fig. 1. Using these spares, the proposed BIRA can achieve a 100% normalized repair rate and a higher repair rate than the conventional spare structure. The explanations for the feature of each spare are given later. In a 3-D memory block, there can be a vertical relationship between each block using spare sharing between dice; there can also be a horizontal relationship within the same die, as shown in Fig. 1. In order to reduce the hardware overhead, a storage structure of the fault collection unit is devised. And an analyzer is developed to exhaustively search every repair case. Although the number of cases required for the exhaustive combinations of the various spares is large, this onerous analysis time can be overcome by simplifying the search. Therefore, the proposed BIRA can rapidly repair a tested memory to the full extent possible with the given spares for any spare structure.
Figure 1: Cost-effective spare structure with many types of spare cells
The proposed BIRA has an expandable spare structure that has a 100% normalized repair rate by searching all the spare allocation cases. Therefore, it is a practical solution for the memory repair, which has expandable spare cell structure. BIRA algorithm for multiple-block memory is proposed. This improves the repair rate of multiple single-die memory. Memories are usually composed of multiple memory blocks or memory banks. Since each memory block has only local spare cells, in order to repair the whole memory, most BIRA algorithms repair each memory block with its own spare cells sequentially. In order to efficiently repair the memory, the proposed BIRA repairs multiple blocks with the help of global spare cells and common spare cells.
Features of the Cost-Efficient Spare Structure:
The cost-efficient spare structure of the memory has various types of spares, as shown in Fig. 1. These types of spares can be used according to their length, the range of their application, and their direction, as shown in Fig. 2. The cost-efficient spare structure looks quite complex.
Figure 2: Definition of the number of each spare
However, the memory is composed of many blocks. The cost efficient spare structure uses the concepts of spare sharing and spare length. It can cause designing of fuses and gates for routing to become a little complex. It may make memory access time and performance of operation degrade. However, improving yield is a more important issue and the complexities of the proposed spare structure can be acceptable to the future memory. As mentioned above, exhaustive searching BIRA can find out every repairable case a many finite allocation cases in the traditional spare structure, and the proposed BIRA, modified CRESTA and BRANCH for the tested memory can also find out every repairable case a many finite allocation cases in the proposed cost-efficient spare structure.
Fig. 2 shows the feature options. The length options refer to the length of the spare. A single spare can only cover a single block. On the other hand, a double spare can cover an adjacent block’s row or column in the same direction as the spare. The single spare is more efficient in terms of the yield per spare area than the double spare; however, BIRA needs more CAM cells to store more faulty information with single spares because it changes the must-repair condition of the blocks, and this change increases the number of must-storing faults to achieve an optimal repair rate. As the number of usable spares in a block increased, the number of must-storing faults also increased. A specific calculation of the number of must-storing faults to achieve the optimal repair rate will be explained along with the proposed CAM structure using an equation. Because of this fact, the overall hardware of BIRA increased, while the yield per hardware overhead of BIRA decreased. Therefore, the structure of the spares should be considered on the basis of the efficiency of the hardware overhead of BIRA and spares.
Proposed CAM Structure:
CAM can use the contented value as an address. Therefore, BIRA can store the faulty information in a cycle in the correct place using the incoming fault; as CAM compares and stores the faulty information in a cycle, BIRA does not interrupt BIST. Therefore, the storage cell of the proposed BIRA is CAM. CAM is connected with BIST, as shown in Fig. 10. BIST provides CAM with fault and test finish information to store faults and determine whether BIRA collects faults or analyzes collected faultsto find a repair solution. The proposed structure of CAM can be divided into two parts. One of the two parts is the pivot CAM (PCAM). PCAM stores the faults that have independent row and column addresses. As mentioned above, the faults are defined as pivot faults. The other part is the nonpivot CAM (NPCAM). NPCAM stores the faults that have the same row or column address as the pivot faults that have been previously stored in PCAM. The reason for which CAM of the proposed BIRA collects faults as the pivot and nonpivot faults is to use the characteristics of the pivot fault in the proposed analyzer.
Figure 3: Pivot CAM
Fig. 3 shows the composition of PCAM. An enable flag shows whether the line of PCAM is occupied by a fault. Next to the enable flag, there are row and column address CAMs for storing the addresses of pivot faults. When the row and column length of a block are Nand M, respectively, CAM should be able to express the full address of the row and column, log 2Nand log 2M, respectively. The block address CAM is to represent the block address of the storing pivot fault. To show the must-repair states on the tested memory, there is mustrepair information, which includes the block row must-flag, block column must-flag, adjacent block row must-flag, and adjacent block column must-flag. For the multiple memory blocks, the must-repair condition is changed.
Figure 4: Nonpivot CAM
Fig. 4 shows the composition of NPCAM. An enable flag shows whether the line of NPCAM is occupied by a fault like the enable flag of PCAM. As the sharing row or column address of the nonpivot needs to be stored with a pivot fault, the duplicated address is also stored. Subsequently, this causes the storage cells to be wasted. Therefore, the proposed NPCAM uses a PCAM pointer and an r/c-type descriptor to express the position of the sharing address. The PCAM pointer represents the position of the sharing PCAM line, and the r/c-type descriptor represents the type of address of NPCAM (i.e., row or column). When the r/c-type descriptor is equal to “1,” the type of sharing address is a column. Otherwise, the type of sharing address is a row. The row or column address should be able to express the maximum lengths of N and M. The block address of the nonpivot should be stored because the block address of a nonpivot fault is not always the same as that of a pivot fault in the case where the nonpivot fault is on the adjacent block.
Proposed Analyzer for the Tested Memory:
As mentioned above, 2-D spare allocation is an NP-complete problem. Thus, exhaustive searching is essential for finding a reparable solution using limited spares. In addition, the cost-efficient spare structure has more variables than the traditional row and column spare structure. The added variables are the length of the spare and the coverable range of the spare. Thus, the analyzer may have to be more complex than the traditional BIRA to consider the added variables.
Figure 5: Proposed analyzer for the target spare structure
Fig. 5 shows the proposed analyzer. It is designed to consider the direction and length of spares. The addresses and the block addresses of the faults saved on PCAM are connected to each pivot row and pivot column of Fig. 7, according to the sequence of the PCAM line. The proposed analyzer uses three signals for exhaustive searching. At first, the proposed analyzer uses the direction-of-spares-selection signal (DSSS) to search every case of the direction selection for each pivot fault. It uses the pivot fault characteristics whereby every pivot fault should be covered by at least one spare, regardless of the direction of the spare. Thus, every bit of DSSS refers to a row or column according to a value “1” or “0.” The length of DSSS is the same as the total number of spares or the number of lines in PCAM used to select a row or column address of the stored pivot faults. Thus, DSSS is connected to each multiplexer (MUX) and chooses every pattern of cases a the pivot faults on the basis of the number of row and column spares.
Figure 6: Block diagram of the proposed RA scheme
The comparison results of RAC and CAC are connected to each of two input OR gates at the bottom of Fig. 5. Thus, the output of the OR gate indicates whether the nonpivot fault is covered. When the output of the OR gate is “0,” the nonpivot fault is uncovered. However, when the output of the ORgate is “1,” the corresponding nonpivot fault is covered. After all, the proposed analyzer outputs uncover_nonpivot_addr, the uncovered nonpivot addresses, and nonpivot_cover_result, the nonpivot cover result, to the redundant analyzer in Fig. 6 to consider a final repair.
Advantages:
- Area coverage is high
Software implementation:
- Modelsim
- Xilinx ISE