Hybrid LUTMultiplexer FPGA Logic Architectures

**Abstract:**

Hybrid configurable logic block architectures forfield-programmable gate arrays that contain a mixture of lookuptables and hardened multiplexers are evaluated toward the goalof higher logic density and area reduction. Multiple hybridconfigurable logic block architectures, both nonfracturable andfracturable with varying MUX:LUT logic element ratios areevaluated across two benchmark suitesusing a custom tool flow consisting of LegUp-HLS, Odin-IIfront-end synthesis, ABC logic synthesis and technology mapping,and VPR for packing, placement, routing, and architectureexploration. Technology mapping optimizations that targetthe proposed architectures are also implemented within ABC.Experimentally, we show that for nonfracturable architectures,without any mapper optimizations, we naturally save up to∼8%area postplace and route; both accounting for complex logicblock and routing area while maintaining mapping depth. Witharchitecture-aware technology mapper optimizations in ABC,additional area is saved, post-place-and-route. For fracturablearchitectures, experiments show that only marginal gains areseen after place-and-route up to∼2%. For both nonfracturableand fracturable architectures, we see minimal impact on timingperformance for the architectures with best area-efficiency.The proposed architecture of this paper is analysis the logic size, area and power consumption using tanner tool.

**Enhancement of the project:**

To design the ALU based on LUTs

**Existing System:**

In this paper, we present a six-input LE based on a4-to-1 MUX, MUX4, that can realize a subset of six-inputBoolean logic functions, and a new hybrid complex logicblock (CLB) that contains a mixture of MUX4s and 6-LUTs.The proposed MUX4s are small compared with a 6-LUT(15% of 6-LUT area), and can efficiently map all{2, 3}-input functions and some {4,5,6}-input functions.In addition, we explore factorability of LEs—the ability tosplit the LEs into multiple smaller elements—in both LUTsand MUX4s to increase logic density. The ratio of LEs thatshould be LUTs versus MUX4s is also explored towardoptimizing logic density for both nonfracturable andfracturable FPGA architectures.

MUX4: 4-to-1 Multiplexer Logic Element:

The MUX4 LE shown in Fig. 1 consists of a 4-to-1 MUXwith optional inversion on its inputs that allow the realizationof any{2,3}-input function, some {4,5}-input functions, andone 6-input function—a 4-to-1 MUX itself with optionalinversion on the data inputs. A 4-to-1 MUX matches the inputpin count of a 6-LUT, allowing for fair comparisons withrespect to the connectivity and intracluster routing.

Naturally, any two-input Boolean function can be easilyimplemented in the MUX4: the two function inputs can betied to the select lines and the truth table values (logic-0orlogic-1) can be routed to the data inputs accordingly.Or alternately, Shannon decomposition can be performedabout one of the two variables—the variable can then feeda select input. The Shannon cofactors will contain at mostone variable and can, therefore, be fed to the data inputs(the optional inversion may be needed).

Figure 1: MUX4 LE depicting optional data input inversions

Logic Elements, Fracturability, and MUX4-Based Variants:

Two families of architectures were created: 1) without fracturable LEs and 2) with fracturable LEs. In this paper, the fracturable LEs refer to an architectural element on which one or more logic functions can be optionally mapped. Nonfracturable LEs refer to an architectural element on which only one logic function is mapped. In the nonfracturable architectures, the MUX4 element shown in Fig. 1 is used together with nonfracturable 6-LUTs. This element shares the same number of inputs as a 6-LUT lending for fair comparison with respect to the input connectivity.

Figure 2: Fracturable 6-LUT that can be fractured into two 5-LUTs with two shared inputs.

For the fracturable architecture, we consider an eight-input LE, closely matched with the adaptive logic module in recent Altera Stratix FPGA families. A 6-LUT that can be fractured into two 5-LUTs using eight inputs is shown in Fig. 2. Two five-input functions can be mapped into this LE if two inputs are shared between the two functions. If no inputs are shared, two four-input functions can be mapped to each 5-LUT. For the MUX4 variant, Dual MUX4, we use two MUX4s within a single eight-input LE. In the configuration, shown in Fig. 3, the two MUX4s are wired to have dedicated select inputs and shared data inputs. This configuration allows this structure to map two independent (no shared inputs) three-input functions, while larger functions may be mapped dependent on the shared inputs between both functions.

Figure 3: Dual MUX4 LE that utilizes dedicated select inputs and shared data inputs.

**Proposed System:**

In the proposed design, ALU is design using non Fracturable and Fracturable LUT. Based on the Fracturable LUT the power consumption of the design is reduced compare to non Fracturable design. The basic introduction of the ALU is given below.

In ECL, TTL and CMOS, there are available integrated packages which are referred to as arithmetic logic units (ALU). The logic circuitry in this units is entirely combinational (i.e. consists of gates with no feedback and no flip-flops).The ALU is an extremely versatile and useful device since, it makes available, in single package, facility for performing many different logical and arithmetic operations. ALU’s comprise the combinational logic that implements logic operations such as AND, OR and arithmetic operations, such as ADD, SUBTRACT.

A number of basic arithmetic and bitwise logic functions are commonly supported by ALUs. Basic, general purpose ALUs typically includes these operations in their repertoires:

Arithmetic operations

- Add: A and B are summed and the sum appears at Y and carry-out.
- Add with carry: A, B and carry-in are summed and the sum appears at Y and carry-out.
- Subtract: B is subtracted from A (or vice versa) and the difference appears at Y and carry-out. For this function, carry-out is effectively a “borrow” indicator. This operation may also be used to compare the magnitudes of A and B; in such cases the Y output may be ignored by the processor, which is only interested in the status bits (particularly zero and negative) that result from the operation.
- Subtract with borrow: B is subtracted from A (or vice versa) with borrow (carry-in) and the difference appears at Y and carry-out (borrow out).
- Two’s complement (negate): A (or B) is subtracted from zero and the difference appears at Y.
- Increment: A (or B) is increased by one and the resulting value appears at Y.
- Decrement: A (or B) is decreased by one and the resulting value appears at Y.
- Pass through: all bits of A (or B) appear unmodified at Y. This operation is typically used to determine the parity of the operand or whether it is zero or negative.

- AND: the bitwise AND of A and B appears at Y.
- OR: the bitwise OR of A and B appears at Y.
- Exclusive-OR: the bitwise XOR of A and B appears at Y.
- One’s complement: all bits of A (or B) are inverted and appear at Y.

(a) (b)

Figure 4: ALU design using non-Fracturable and Fracturable LUT.

In non fracturable LUT design based ALU is shows in fog 4(a) and Fracturable LUT based ALU design is shows in the figure 4(b).

**Software implementation:**

- Tanner EDA
- ALTRA Quartus