Scalable Device Array for StatisticalCharacterization of BTI-Related Parameters
Abstract:
A device array circuit, scalable in terms of the number of transistors used, is proposed. The proposed array facilitates accurate and simultaneous bias voltage application to a large number of devices, making it suitable for the measurement based statistical characterization of device degradation, known as bias temperature instability. Using the proposed array, the degradation measurement of thousands of transistors is made possible in a practical amount of time. The experimental results show that the defect-centric model can approximate the statistical variation in magnitudes of threshold voltage shifts (delta- VTH) and that the variance of delta- VTHbears an inverse relationship to the channel areas of transistors. The degradation variability underac stress conditions is also presented for the first time.The proposed architecture of this paper analysis the logic size, area and power consumption using tanner tool.
Existing System:
The measurement technique for NBTI is important becausegood experimental data are vital for modeling the degradationand for studying the mechanism of NBTI. However, it is adifficult task because the degradedVTH starts to recover assoon as the stress is released.Various circuits have been proposed to measureBTI-induced device degradation. They can be categorizedby whether the off-chip equipment is required or not.A representative example of the stand-alone circuit that doesnot depend on the off-chip equipment is proposed,in which the beat frequency of two ring oscillators (ROs)is utilized to amplify the small VTH differences caused bydegradation. These types of circuits are suitable for buildingan on-chip degradation sensor. However, VTHs cannot beobtained directly, so that translation from RO frequencyto VTH is required. Because the oscillation frequencyof the RO depends on all transistors in the RO, it isimpossible to know the degradation of a particular transistor.Considering that our objective is to provide a TEG circuitfor NBTI modeling, it is not suitable to use the RO-likestructure.
In order to characterize the degradation of a single transistor,assistance of off-chip equipment is necessary to directlymeasureVTHs or leakage currents. Examples of this type of circuit are found. Trying to capture the fastrecovery by SMUs, the use of an opamp-based current sourceis proposed to shorten the settling time of the output voltage. Another approach is the on-the-fly technique.Instead of directly measuring the VTH of a transistor, thechange of drain current is measured while applying the stressvoltage.These techniques are developed to measure a few transistorsat most. However, in modern LSI designs, the variability ofthe degradation should also be taken into account. When NBTImeasurements of many transistors are involved, very longmeasurement time becomes an obstacle. Even if theVTHshiftis accelerated under a high temperature and a high electricfield, it takes hours or even days to cause a notableVTHshift.In order to measure NBTI on a large number of transistorswithin a practical period of time, the stress and recoveryperiods of the transistors have to be parallelized.
Figure 1: (a) Concept of stress overlapping realized in BTIarray. The DUTs are stressed or recovered in parallel and exclusively enter into the measurement mode to share the proving pad and an SMU. (b) Improved timing accuracy realized by BTIarray2. Periods under which stress or recovery biases are applied to DUTs are equalized.
Fig. 1(a) shows the concept of the time overlappingtechnique introduced; the circuit realization is calledBTIarray. The solid and dashed lines represent that the corresponding DUT is under stress and recovery bias modes,respectively. The small boxes represent that the correspondingDUT is under a measurement mode. We can achieven-foldreduction of the total measurement time when measuringn-DUTs using the BTIarray because stress period is usuallya few orders of magnitude longer than the time required foracquiring aVTHsample.
Disadvantages:
- Accuracy is less
Proposed System:
We propose ascalablearray structure, namedBTIarray2, which accommodates thousands of DUTs forBTI-measurement while maintaining comparable accuracy toBTIarray. The experimental results show that degradationsof 3996 DUTs are successfully measured with BTIarray2,which is designed and fabricated using a 180-nm CMOStechnology. The statistical properties of BTI-induced devicedegradation for thousands of transistors are also investigatedfor the first time.
Circuit Structure:
Fig. 2 shows the schematics of a DUT and pass-gateswitches for bias voltage selection. Constant supply voltagesare given toVSS, VSTR, VREC, VDD,andVBIAS. The constantcurrent is given toVCCfor VTHmeasurement. Here,VDDisthe supply voltage and VSSis 0 V.In the recovery mode, switches sw0, sw3, sw5, sw8, andsw11 are closed. Here, VRECis a recovery voltage, which isgreater than or equal toVDD.In the stress mode, switches sw1, sw4, sw5, sw8, and sw11are closed to give the DUT a negative stress. Here,VSTR isstress voltage, which is negative compared withVDD.VTH is measured using the constant-current method.In the measurement mode, switches sw0, sw2, sw6, sw7, sw9,and sw10 are closed. While constant current is forced to theselected DUT through sw9 and sw10, the voltage that appearsat the source node of the DUT,VMis copied to a PAD terminalthrough an on-chip impedance converter to be measured usingan external digital multimeter (DMM).During the measurement, the constant voltage near theVTHof the DUT is given to the nodeVBIASto mitigate the impactof leakage current. The red dashed line in Fig. 2(c) shows thepath along which the leakage current flows in the BTIarray.The source terminal voltage of the DUT under stress modeis VDD, whereas that of the DUT in measurement mode isits VTH.
Figure 2: Schematics of (a) DUT and (b) switch configurations. (c) Leakage current paths.
The voltage difference between the end terminals ofswitches sw6 and sw9 induces leakage current to flow fromVDDinto the DUT even when the switches are turnedOFF.Theleakage current from the stress-mode DUT blocks collectivelyflows into the DUT under measurement, making it larger thanwhat has to be given in the constant current method. Althoughthe leakage current of a switch is several orders of magnitudesmaller than the constant current, when thousands of DUTsare integrated in an array, a higher voltage than the actualVTHwill be measured. Switches sw7, sw8, sw10, and sw11 areused to resolve this issue without compromising the number ofDUTs in the array. By applying a voltage at the terminalVBIAS,the voltage difference between two terminals of switches sw6and sw9 can be made sufficiently small such that no leakagecurrent flows into the DUT. Unavoidable leakage current atsw10 flows from VDDinto VBIAS[see the red solid line inFig. 2(c)], so it never flows into the DUT. With this assistivecircuit structure, which provides the alternative current path,the scalability of the proposed array can be greatly enhanced.
Figure 3: Block diagram of a DUT block and the peripheral circuits
Fig. 3 shows the construction of a DUT block. Here,VlocalMandVlocalCCin Fig. 3 are connected to VMandVCCin Fig. 2,respectively. The mode switching is realized by the controllogic. An FF is equipped with each DUT block to store thecurrent bias condition. The output nodeVglobalMis connected toa PAD through an impedance converter. The switches sw0 andsw3 are closed when a DUT on a corresponding column is inthe measurement mode. When no DUT on the correspondingcolumn is selected for measurement, switches sw1 and sw2are closed so that the bias voltage VBIASis given to VlocalCCand VlocalM.
Advantages:
- Accuracy is high
Software implementation:
- Tanner tool