Fast Automatic Frequency Calibrator Using an Adaptive Frequency Search Algorithm
Abstract:
A new adaptive frequency search algorithm (A-FSA) is presented for a fast automatic frequency calibrator in wideband phase-locked loops (PLLs). The proposed A-FSA optimizes the number of clock counts for each frequency comparison cycle, depending on the difference between the target frequency and the PLL output frequency, as opposed to a binary frequency search algorithm (B-FSA), where the frequency search time per cycle is fixed. This eliminates unnecessary clocking times during the frequency comparison process, and thus reduces the total PLL lock time. The additional circuitry needed for A-FSA is only a simple counter controller, thus minimizing hardware overhead. To verify the effectiveness of the proposed algorithm, two wideband PLLs are designed and simulated using a 65-nm CMOS technology: one with B-FSA, and the other with A-FSA. The latter achieves a lock time faster than the former by at least a factor of 2, even under worst case conditions The proposed architecture of this paper analysis the logic size, area and power consumption using Tanner tool.
Existing System:
The phase-locked loop (PLL) is one of the essential building blocks of radio frequency (RF) transceivers for portable wireless devices. To reduce the power consumption and/or cost of such transceivers, while supporting multiband communication standards, it is desirable to design a single wideband PLL. Because of the stringent phase noise requirements, PLLs in RF applications typically employ an LC-tank based voltage-controlled oscillator (LC-VCO). However, if a single capacitor is only used in the LC-tank for frequency tuning, it is difficult to achieve wide operating frequency bands. To overcome this difficulty, switched capacitor banks (cap-banks) have been widely used in LC-VCOs, with the cap-bank capacitance being digitally controlled to generate multiple subband frequency tuning curves. Another advantage of this technique is that the VCO gain (KVCO) is lowered for a given PLL tuning range, which helps improve phase noise performance.
Figure 1: Overall structure of an AFC-based wideband PLL
Fig. 1 shows a cap-bank-based wideband PLL with an automatic frequency calibrator (AFC). The AFC and cap-bank perform coarse frequency tuning by searching for the subband tuning curve closest to the target frequency. During this coarse tuning, the analog VCO input VCTRL is connected to a fixed voltage, typically equal to half the supply voltage (VDD/2). Fine frequency tuning is then accomplished by an ordinary PLL locking process, which is performed by a phase frequency detector, a charge pump, a low-pass filter, a feedback frequency divider, and a VCO.
CONVENTIONALB-FSA-BASEDAFCs:
Fig. 2(a) shows the frequency tuning curves of a wideband VCO with an example 4-bitcap-bank. The VCO has 16 subband tuning curves. During coarse frequency tuning, the VCO control voltage (VCTRL) is set to be equal to half the supply voltage (VDD/2). The frequency difference between neighboring curves is defined as the frequency resolution (fRES). The B-AFC starts a calibration process from the center curve, and determines whether the absolute difference between the target frequency (fT) and VCO frequency (fVCO), |∆f|, is smaller or larger than half the fRES. If|∆f| <fRES/2, the AFC holds the current cap-bank code. Otherwise, it shifts the code to the middle curve of the upper or lower side, as shown in Fig. 2(a), depending on the frequency comparison result. This process repeats until the least significant bit of the cap-bank code is determined. For a precise analysis of the B-FSA and a comparison with the proposed A-FSA operation in later sections, we introduce a frequency holding window (fH), which is a range for|f|to make the AFC hold the current cap-bank code until the next frequency search begins.
Figure 2 : Example of a B-AFC operation. (a) Frequency versus control voltage. (b) Transient responses.
Fig. 3 shows the implementation of a conventional B-AFC, which consists of two counters, a tristate digital comparator, and a finite state machine (FSM). One counter counts M and (M+1) rising edges of the PLL reference input withfREF, and the other counter counts Mfalling edges of the feedback signal with fDIV=fVCO/N,whereNis the PLL feedback frequency divide ratio for the target frequency. Note that during the coarse frequency tuning process, the AFC adjusts the value of the fVCOso as to make fDIVas close to fREF as possible. The timing information related to the three edges is sent to the tristate digital comparator, and the back-end FSM controlsthe cap-bank code.
Figure 3: Conventional B-AFC structure
Disadvantages:
- Speed is low
- Area coverage is high
Proposed System:
In this paper, we propose a new A-FSA, where the number of clock counts for each frequency comparison is optimized, thus reducing the cap-bank calibration time. Capitalizing on the fact that the AFC calibration time is inversely proportional to the frequency holding window fHin (10), the A-FSA uses a large fHvalue for the first frequency comparison, and narrows down fHfor the subsequent frequency comparisons.
Fig. 5 is an example that shows a comparison of the conventional B-FSA and the proposed A-FSA processes for a 4-bit cap-bank calibration. The cap-bank frequency curve closest to the target frequency fT is assumed to be the one corresponding to the code 5. Fig. 5(a) shows the case of the B-FSA case, where the frequency holding window fH is kept constant for all frequency comparisons and fixed to fRES. Two neighboring frequency curves are used for determining each bit in the cap-bank. After the first frequency comparison, the cap-bank code shifts down from 8 to 4, and the VCO frequency decreases by 4· fRES. Here, it should be noted that the VCO frequency change (4· fRES) is much larger than the frequency holding window (fRES). This implies that the AFC takes an unnecessarily long time when determining the most significant bit in the cap-bank. Even though the discrepancy between the VCO frequency change and the frequency holding window decreases in the subsequent frequency comparisons, this wasted time apparently exists and increases the calibration time of the B-FSA.
Figure 4: Operational examples for the case of the final code of 5. (a) Conventional B-FSA. (b) Proposed A-FSA.
Fig. 5(b) shows the proposed A-FSA operation. Rather than using a constant fH as in the B-FSA, the A-FSA adjusts frequency holding windows to 7· fRES,3· fRES,andfRES, in the first, second, and final frequency comparisons, respectively. This enables faster frequency comparison by using fewer clock counts than in the B-FSA. In the first frequency comparison, the target frequency fT is within the frequency holding window, thus the cap-bank code is held at 8. The code then shifts down to 6 after the second comparison, because the target frequency is below the frequency holding window (3· fRES) around fVCO. After the third frequency comparison, the cap-bank code finally becomes 5. The advantage of the A-FSA is that it enables post-correction of potential frequency search error in the preceding frequency comparisons. This is because the cap-bank code in the A-FSA can be changed in the subsequent frequency comparisons whenever needed, as opposed to that in the B-FSA, which is kept constant once the VCO frequency is within the frequency holding window.
The proposed A-FSA can be implemented using a B-FSA with an additional digital count value controller (DCVC), as shown in Fig. 8(a). The clock count value MIN is divided to MA−FSA by the DCVC depending on the capbank bit being determined and fed into two clock counters. Fig. 6(b) shows the timing diagram of the DCVC.
Figure 5: (a) Implementation of the proposed A-AFC. (b) Timing diagram of the DCVC for 4- and 5-bit cap-bank calibrations
Advantages:
- Speed is high
- Area coverage is low
Software implementation:
- Tanner tool