Low-Power Design for a Digit-Serial PolynomialBasis Finite Field Multiplier UsingFactoring Technique

**Abstract:**

In CMOS-based application-specific integrated circuit (ASIC) designs, total power consumption is dominated by dynamic power, where dynamic power consists of two major components, namely, switching power and internal power. In this paper, we present a low-power design for a digit-serial finite field multiplier in GF(2^{m} ). In the proposed design, a factoring technique is used to minimize switching power. To the best of our knowledge, factoring method has not been reported in the literature being used in the design of a finite field multiplier at an architectural level. Logic gate substitution is also utilized to reduce internal power. Our proposed design along with several existing similar works have been realized for GF(2^{233})on ASIC platform, and a comparison is made between them. The synthesis results show that the proposed multiplier design consumes at least 27.8% lower total power than any previous work in comparison The proposed architecture of this paper is analysis the logic size, area and power consumption using tanner tool.

**Existing System:**

Binary extension field, denoted by GF(2^{m}), is veryattractive for hardware implementation, because it offers carryfree arithmetic. Multiplication operation has been paid mostattention by researchers, because addition is simply bitwiseXORoperation between two field elements, and the morecomplex operations, inversion, can be carried out with afew multiplications. In GF(2^{m}), there are various methodsto represent field elements, such as polynomial basis (PB),normal basis, and dual basis. PB is probably the most popularly used basis, because it is adopted as one of the basischoices by organizations that set standards for cryptographyapplications. Thus, a large number of architecturesfor efficient implementation of PB finite field multipliershave been proposed. In addition,new representations basedon PB called shifted PB (SPB) and generalized PB have been proposed for efficient implementation of multipliersover GF(2^{m}).

The choice of the irreducible polynomial p(x) affectsthe complexity of a finite field multiplier. Various types ofirreducible polynomials include trinomials, pentanomials, allone polynomials, and equally spaced polynomials. Standardorganizations recommend irreducible polynomials with lessnumber of nonzero terms (irreducible trinomials and pentanomials) for practical use as these types of irreduciblepolynomials can provide multipliers with lower complexity.PB finite field multiplier architectures can be categorizedinto bit-serial, bit-parallel, and digit-serialarchitectures. Bit-parallel structure is fast, but it is expensivein terms of area. In EC cryptography, the binary extensionfield size,m, is required to be on the order of 10^{2}, and thus abit-parallel structure requires a very high I/O bandwidth, whichis usually not available in the small portable and wirelessdevices. Bit-serial architecture is area efficient, but it is tooslow for many applications. Power optimization were alsoconsidered in some of these works.

**Disadvantages**:

- High power consumption

**Proposed System:**

A factoring technique is adopted in design of a digit-serial PB multiplier in GF(2m). To the best of our knowledge, a factoring method has not been reported in the literature being used in the design of a finite field multiplier at an architectural level. A logic gate substitution technique is also used in our design to reduce the internal power consumption of the proposed digit-serial multiplier. The synthesis results show that our new design has both the lowest dynamic power consumption and the lowest total power consumption a several similar existing works.

Binary Extension Field GF(2^{m}):

A finite field is defined as a set of finite many elements, where addition and multiplication are the operations defined on the set. A binary extension field, GF(2m), is generated by a degree mirreducible polynomial, p(x) =xm+pm−1xm−1+···+p2x2+p1x+1, where pi is either 0 or 1. p(x) also specifies a PB{1,x,x 2 ,…,x m−1}. Each element of GF(2m) can be represented as a polynomial of degree at mostm−1 over GF(2m) with respect to the PB. For instance, an element A∈GF (2m) can be expressed as

A(x)=am−1xm−1+am−2xm−2+···+a2x2+a1x+a0(1)

With

ai∈GF(2), 0≤i ≤m−1.

Multiplication of two field elementsA(x)andB(x)of thebinary extension field can be given by

C(x)=A(x)B(x)modp(x). (2)

Digit-Serial PB Multiplication:

In digit-serial multiplication, the bits of one operand aredivided into digits of sizekwhile the bits of the other inputoperand are processed in parallel. Only one digit of the firstoperand is accessible in each clock cycle.

Power Dissipation for CMOS-Based Circuits:

Power consumption in a CMOS-based design contains twomajor components: static power and dynamic power.For a CMOS-based design, dynamic power plays a dominantrole in the total power consumption.

Proposedlow-powerdesign of adigit-serialmultiplier inGF(2^{m}):

Multiplier Architecture:

An architecture diagram for the proposed digit-serial PBmultiplier in GF(2m) is shown in Fig. 2. There are threemodules, as shown in Fig. 2, namely,k×mmultiplier, constantmultiplier, and field adder.

- k×mmultiplier takes one operandBofm-bit and the other operand Ajofk-bit. Note that Aj changes for different clock cycles j. Thus, it has higher switching activity compared with operand B. A straightforward realization of this module was used. For the comparison purpose, it is given in Algorithm 1. Note that a modification to this algorithm using a factoring method is proposed in Section III-B. The three steps in Algorithm 1 are, respectively,realized with the circuit blocks from left to right, as shown in Fig. 3(a).
- Constant multiplier module realizes multiplication between a field element and the constant x
^{k}. - Field adder module implements finite field addition using m two-input XOR gates formed as a one-layer network.

**Advantages:**

- Low power consumption

**Software implementation:**

- Tanner EDA