An On-Chip Monitoring Circuit for Signal-IntegrityAnalysis of 8-Gb/s Chip-to-Chip Interfaces WithSource-Synchronous Clock
Abstract:
This paper presents an on-chip monitoring circuit (OCMC) for analyzing the signal integrity of high speed signals for a chip-to-chip interface with a source synchronous clocking scheme. The proposed OCMC consists of a fractional-N phase-locked loop (PLL)-based frequency synthesizer, a high-bandwidth track-and-hold circuit, and a 10-bit analog-to-digital converter (ADC) to implement a subsampling scheme. The proposed fractional-N PLL-based frequency synthesizer improves the time jitter accumulated in a voltage controlled oscillator using a fractional frequency divider operated by an eight-phase clock. The bandwidth of the track-and hold circuit is designed to be 6 GHz, using inductive peaking realized through a source follower. The OCMC samples 49 points over two unit intervals of a high-speed input signal when the frequency multiplication of the frequency synthesizer is 6.125/6. The 10-bit ADC uses the architecture of a pipelined successive approximation register ADC to reduce the power consumption and chip area. The proposed OCMC is implemented with 65-nm CMOS technology and a 1.2 V supply. The 8-Gb/s chip-to-chip interface signal is reconstructed with time and voltage resolutions of 5.1 ps and 1.17 mV, respectively. The proposed architecture of this paper analysis the logic size, area and power consumption using tanner tool.
Existing System:
The amount of data required in applications such asdisplays, communications, and data processing hasincreased greatly. Wide input–output (I/O) technologiesincluding the 3-D die stack and silicon-carrier interposer arebeing used to achieve a high bandwidth as the speed per pin ofthe chip-to-chip interface increases. Interface analysessuch as the bit error rate (BER) and signal integrity (SI)are still important in these cases because the interface speedusing wide I/O technologies constantly increases. Althoughexternal test equipment can be generally used to measure theBER and SI, its use causes many difficulties regarding thevisibility, accuracy, and complexity of the high-speed interface as the data rate of the chip-to-chip interface increasesto more than several gigabits per second. Furthermore,the external test equipment cannot be directly used to analyzethe functions or performances of the high-speed interface whenthe chip-to-chip interfaces with 3-D die stacks or siliconcarrier interconnects are assembled. In this case, the BERand SI can be measured using electron-beam or lase-voltageprobing.
However, these methods are extremely expensive; thismakes it difficult to evaluate the performance of the highspeed interface. Previous literatures have reported onan on-chip oscilloscope, which captured the eye diagram andjitter histogram of the high-speed signal. These conventionalon-chip oscilloscopes require an external clock and a referencevoltage controlled by the automatic test equipment (ATE) toacquire the Shmoo plot or the BER plot. Furthermore, theon-chip oscilloscope circuits reported stillrequire external test sequences from the ATE, and they generate the reference voltage and sampling clock using additionalcircuits on the chip.
Disadvantages:
- lowspeed
- less band width
Proposed System:
Proposedon-chipmonitoringcircuit:
The proposed OCMC uses a subsampling scheme todirectly acquire a high-speed input signal or reconstruct itseye diagram, while it uses an ADC with a lower samplingrate compared with the frequency of the input signal. Forthe subsampling operation, the sampling operation should beperformed one time per cycle or many cycles of the inputsignal. Furthermore, the sampling point must rotate from cycleto cycle so that the sampling clock (TSAMP_CLK) samplesmany equally spaced points to acquire the eye diagram.
Figure 1: Conceptual time diagram of subsampling scheme.
Fig. 1 shows an example of the timing diagram for thesubsampling scheme when the value ofMis set as 1. The inputsignal (SIGNAL)is sampled repeatedly at equally distributedNpoints out of everyN−1cycles,whereNis seven.
Architecture offrequencysynthesizer:
The proposed frequency synthesizer usesCLOCKfor asource-synchronous clocking scheme as its reference clock.In this paper, it is basically designed using architecture basedon a PLL instead of a DLL to filter the dynamic noise ofCLOCK. A phase-locked loop (PLL) with a sigma-delta modulator can generally be used as a frequency synthesizer. This architecture is suitable for generating a high-frequencyclock; however, it can cause a relatively large jitter whengenerating a low-frequency clock. A conventional frequencysynthesizer can be implemented using a fractional-NPLL witha frequency divider composed of flip-flops for the subsamplingscheme of the proposed OCMC, as shown in Fig. 2(a). It usesdivide-by-48 and divide-by-49 frequency dividers for the inputclock and voltage-controlled-oscillator (VCO) feedback clock,respectively, when the value of N issetto49forthetime resolution of the reconstructed data of 5.1 ps accordingto (2). Furthermore, M/2of (4) is set as 16 using twofrequency dividers, prefrequency divider and postfrequencydivider which divide the frequency by four for the inputand output clocks. Thus, the frequency synthesizer outputs aSAMP_CLKof 127.6042 MHz from an input clock (CLOCK)of 2 GHz. As a result, the proposed OCMC can repeatedlysample at 49 points of data over two UIs of the input signalwith an 8-Gb/s data rate. However, this architecture increasesthe time jitter in the output clock owing to the accumulationof VCO noise as the frequency division ratio of the VCOfeedback clock increases. This is explained in the timingdiagram shown in Fig. 2(b).
Figure 2: Conventional frequency synthesizer and pre/post frequency dividers for 49-point sampling. (a) Block diagram. (b) Accumulated time jitter of VCO_CLK
Fig. 3(a) shows a block diagram of the proposed frequencysynthesizer. The frequency dividers for the reference clock andthe VCO feedback clock are proposed to minimize the timejitter by reducing the path delay in the clock. Furthermore,the frequency divider for the VCO feedback clock can performfractional frequency division using a multiphase clock suppliedfrom the VCO. Thus, the proposed frequency synthesizerreduces the time jitter by minimizing the frequency divisionratio, as shown in Fig. 3(b). In this paper, the VCO generatesan eight-phase clock to implement the proposed fractionalfrequency division by 6.125 for the VCO feedback clock. TheVCO uses a ring oscillator to reduce the area of the proposedfrequency synthesizer although a ring oscillator has a relativelylarge time jitter compared with an LC oscillator. It consists offour delay cells based on pseudo-differential current starvedinverters. Meanwhile, the time delay differences aeach eight-phase clock in theproposed frequency synthesizercan cause the deterministic time jitter at the output clock.To minimize this deterministic time jitter, four differentialdelay cells should be carefully designed for the matchedlayout, and the characteristic of VCO should be verified byperforming the simulation including the expected parasiticcomponents.
Figure 3: Proposed frequency synthesizer and pre/post frequency dividers for 49-point sampling. (a) Block diagram. (b) Improvement of accumulated time jitter of VCO_CLK
Advantages:
- High speed
- More band width
Software implementation:
- Tanner tool