Soft Error Rate Reduction of Combinational Circuits Using Gate Sizing in the Presence of Process Variations

**Abstract:**

Soft errors in combinational logic circuits are emerging as a significant reliability concern for nanoscale VLSI designs. This paper presents a novel sensitivity-based gate sizing methodology to reduce the soft error rate (SER) of combinational circuits in the presence of process variations. The proposed method is based on modeling the statistics of SER of the circuit gates as a random variable to formulate a statistical optimization problem. A backward traversing algorithm with capability for incremental analysis is developed for computing the distribution of circuit gates of SER random variables. We present a gate resizing algorithm in which the gates with the most contribution to the circuit SER are selected in a candidate set using a statistical ordering approach. The proposed algorithm trades off SER reduction and area overheads. The experimental results show that using the proposed methodology, the circuit statistical SER can be reduced by up to 56.4% compared with the 14.8% SER reduction of a circuit obtained using the worst case methodology at the expense of 10% area overhead under 10% process variation ratio. The results also show that the proposed method achieves about 40% more SER reduction compared with that obtained using closed-form analysis for statistical soft error rate estimation (CASSER), the most recently published similar work, in the same experimental conditions. Comparing the runtime of the proposed optimization algorithm with the optimization based on CASSER, it is observed that the proposed method is two orders of magnitude faster than CASSER due to its incremental analysis property. The proposed architecture of this paper analysis the logic size, area and power consumption using Tanner tool.

**Existing System:**

In addition to variation-aware SER estimations in SRAM cells [38], [39], multiple approaches that consider process variations in the SER of a digital circuit have emerged recently. In [19], the effects of process variations on the SET pulsewidth distribution of inverters fabricated by silicon-on-insulator technology are obtained. A statistical SER analysis method based on modified response surface modeling and artificial neural network modeling is proposed in [20]. Ramakrishnan et al.[18] modeled the generation and propagation of transient faults as a function of gate delay. Later, the work in [21] used a symbolic approach to present a variation-aware transient fault modeling. In [22], quality table-based cell models were proposed to estimate SER considering process variations while quasi-random sequences were used to shorten the runtime. In [23], a statistical learning algorithm is proposed to build support vector machine models to deal with transient faults in the presence of process variations.

A framework named CASSER, presented in [11], is an approach for SER analysis in which a transient pulse was partitioned into two transition signals and these signals were propagated in a block-based fashion similar to the statistical static timing analysis. An SSER estimation method serves two primary purposes. The first is to determine whether a design meets the soft error robustness requirements for signoff, a goal that is (barely) met at the tail end of a design project. The second is to provide feedback and diagnostics to aid designers in optimizing soft error robustness. Although there are some SSER estimation methods offering valuable insights for the first purpose, they suffer from various problems that reduce their applicability to the second purpose of SSER optimization algorithms. Most of them are based on Monte Carlo approaches, which are very time consuming. Hence, there is a clear need for the static SSER estimation method for optimization applications. Recently, a static method called CASSER is proposed. However, it suffers from two main problems.

1) Although CASSER considers process variations in its SER estimations, it treats the SER as a deterministic value instead of a statistical random variable. This simplification shows its catastrophic effect when the obtained deterministic SER values are used in SER optimization flow.

2) CASSER depends on re-propagating SETs along the circuit in re-estimating SSERs resulting in a time consuming process in the optimization approaches based on CASSER. Hence, CASSER cannot be applied efficiently in the SSER optimization flow. To the best of our knowledge, this is the first work that reduces SSER of a combinational circuit in the presence of process variations.

**Disadvantages**:

- Speed is low

**Proposed System:**

Backward Analysis Concept:

In this section, we present the backward analysis concept for timing constraint extraction. We will extend this analysis to consider all triple constraint in the next section. The SET occurring in circuit node i should satisfy the setup time and hold time conditions in order to be latched at FF j. We traverse the circuit net list backward to determine the necessary timing constraints that should be met by generated SETs at the circuit nodes. In this approach, the conditions for the parameters of the SET at circuit node i required to be latched in FF j are determined as follows.

Figure 1: Concepts of STC and HTC.

1) The SET that occurred in circuit node i should occur before a specific time instance such that the constraints of setup time of FF at j are satisfied by the SET in i [setup time constraint (STC) as shown in Fig. 1].

2) The SET that occurred in circuit node i should continue unto a specific time instance such that the constraints of hold time of the FF at j are satisfied by the SET in i [hold time constraint (HTC) as shown in Fig. 1].

Fig. 2 shows the concepts of STC and HTC parameters for various cases in a circuit. For a gate directly connected to FF j, i.e., G1, STC and HTC are equal to Tclk −ts and Tclk+th, respectively.

Figure 2: Example of STC and HTC for different cases in a circuit.

Statistical Vulnerability Window:

Considering three (logical, electrical, and timing) masking factors, we introduce SVW, which is an inference of the requirements that should be met by an SET in a given circuit node in order to be latched as a soft error.

1) SVW Parameters: Conceptually, SVW is a metric that shows the vulnerability of a circuit node to the SETs, which can occur in it, and may finally result in soft errors in an FF. We define the SVW as a four-ordered parameter set (output ID, starting time, ending time, and sensitization probability).

2) SVW Parameter Computation: In order to calculate the SVWs for all circuit nodes, we first calculate the parameters of the SVW for the gates directly connected to the FFs and then traverse the circuit graph backward and compute SVW parameters for all other circuit nodes.

3) Computation of P_{sen} is similar to that in the gate error model used in [37] using Boolean difference calculus.

**Advantages:**

- Speed is high

**Software implementation:**

- Tanner tool