by nexgentech | Oct 24, 2017 | ieee project
COMEDI: Combinatorial Election of Diagnostic Vectors From Detection Test Sets for Logic Circuits Abstract: Although the modern automatic test pattern generation (ATPG) tools can efficiently produce near-optimal test sets with high fault-coverage for a...
by nexgentech | Oct 24, 2017 | ieee project
Publicly Verifiable Watermarking for Intellectual Property Protection in FPGA Design Abstract: Watermarking as a novel intellectual property (IP) protection technique can protect field-programmable gate array IPs from infringement. However, existing watermarking...
by nexgentech | Oct 24, 2017 | ieee project
A 0.45 V 147–375 nW ECG Compression ProcessorWith Wavelet Shrinkage and AdaptiveTemporal Decimation Architectures Abstract: This paper presents a real-time electrocardiogram (ECG) data compression processor with improved energy efficiency while maintaining high...
by nexgentech | Oct 24, 2017 | ieee project
10T SRAM Using Half-VDDPrecharge andRow-Wise Dynamically Powered ReadPort for Low Switching Powerand Ultralow RBL Leakage Abstract: We present, in this paper, a new 10T static random access memory cell having single ended decoupled read-bitline (RBL) with a 4T read...
by nexgentech | Oct 24, 2017 | ieee project
An On-Chip Monitoring Circuit for Signal-IntegrityAnalysis of 8-Gb/s Chip-to-Chip Interfaces WithSource-Synchronous Clock Abstract: This paper presents an on-chip monitoring circuit (OCMC) for analyzing the signal integrity of high speed signals for a chip-to-chip...
by nexgentech | Oct 24, 2017 | ieee project
Scalable Device Array for StatisticalCharacterization of BTI-Related Parameters Abstract: A device array circuit, scalable in terms of the number of transistors used, is proposed. The proposed array facilitates accurate and simultaneous bias voltage application to a...
by nexgentech | Oct 24, 2017 | ieee project
A Single Channel Split ADC Structure for DigitalBackground Calibration in Pipelined ADCs Abstract: A digital background calibration technique based on the concept of split analog-to-digital converter (ADC) structure is proposed for pipelined ADCs to correct the gain...
by nexgentech | Oct 24, 2017 | ieee project
A 2.5-ps Bin Size and 6.7-ps ResolutionFPGA Time-to-Digital Converter Basedon Delay Wrapping and Averaging Abstract: A high-resolution time-to-digital converter (TDC) implemented with field programmable gate array (FPGA) based on delay wrapping and averaging is...
by nexgentech | Oct 24, 2017 | ieee project
Coordinate Rotation-Based Low ComplexityK-Means Clustering Architecture Abstract: In this brief, we propose a low-complexity architectural implementation of the K-means-based clustering algorithm used widely in mobile health monitoring applications for unsupervised...
by nexgentech | Oct 24, 2017 | ieee project
Dual-Quality 4:2 Compressors for Utilizing inDynamic Accuracy Configurable Multipliers Abstract: In this paper, we propose four 4:2 compressors, which have the flexibility of switching between the exact and approximate operating modes. In the approximate mode, these...
