A Single Channel Split ADC Structure for DigitalBackground Calibration in Pipelined ADCs
Abstract:
A digital background calibration technique based on the concept of split analog-to-digital converter (ADC) structure is proposed for pipelined ADCs to correct the gain error induced by the capacitors mismatch and finite dc gain of the residue amplifiers and nonlinearity of the residue amplifiers. In the proposed technique, one of the channels in split ADC structure is virtually implemented by using two extra comparators in each ADC’s stage and an interpolation filter to eliminate the mismatch between channels. Several circuit-level simulation results in the context of a 12-bit 100-MS/s pipelined ADC are provided to verify the usefulness of the proposed calibration technique. The simulation results show 51-dB signal-to-noise and distortion ratio and 65-dB spurious free dynamic range improvement, respectively, in comparison with the noncalibrated ADC. The proposed architecture of this paper analysis the logic size, area and power consumption using Tanner tool.
Existing System:
Several digital calibration methods have been presented in theliterature. The correlation of the ADC’s digital output witha pseudorandom sequence, which acts like an offset in the ADC,is calculated to correct the gain error and nonlinearity of the amplifier. The histogram of the ADC around the decision points of thesub-ADC is investigated to address the gain error. The main problemof the pseudorandom and histogram-based methods is that theyrequire a long time to converge or lots of digital processing. To avoidthese problems, equalization-based techniques have been presented inthe literature. A slow but accurate ADC is usedto calibratethe pipelined ADC and a reference digital-to-analog converter (DAC)along with the least mean square (LMS) algorithm is utilized.Equalization-based techniques benefit from the fast convergence timeunlike the pseudorandom-based schemes. However, they need anaccurate reference resulting in the analog design complexity andmore power consumption. A semiequalization-based techniqueis used to reduce the convergence time of split ADC structures.Regarding this method, an unknown gain is added in the path ofinput signal to make a replica path for the pipelined ADC. Thisreplica path and an interpolation filter are used to extract the gainerror and nonlinearity of the amplifier. However, this increases theanalog design complexity and also the calibration coefficients.
Figure 1: Circuit implementation of a 1.5-bit stage
Figure 2: Effect of circuit non-idealities in the (a) MDAC transfer function
A circuit implementation of commonly used 1.5-bit stage is shown in Fig. 1. This scheme offers the same gain property for the inputsignal and the DAC path. Hence, the capacitor mismatch and theamplifier gain error can be considered at the same way. In the restof this brief, all signal voltages are normalized byVreffor simplicity.Fig. 2(a) shows the stage transfer function that has two discontinuities at the decision points,±0.25. Due to the circuit nonidealities,the transfer function deviates from the ideal case and some missingcodes appear at the ADC output around the decision points. Fig. 2(b)shows the ADC transfer function with a non-ideal first stage and anideal backend ADC. Owing to the circuit nonidealities in the firststage, some missing codes appear around±0.25.
Figure 3: Stage and its digital calibration model
The first stage and its digitaldomain calibration model are shown in Fig. 3. It should be mentionedthat the ADC calibration starts from the last stage and ends in thefirst stage. Therefore, in the calibration ofith stage, the latter stageshave been calibrated already and they are used as an ideal backendADC to produce the digital equivalent of this stage’s output,Dres.
Disadvantages:
- Power consumption is high
- Area coverage is high
Proposed System:
a calibration technique based on the split ADC structure is proposed by using a single ADC and some extra comparatorswith an interpolation filter as the virtual ADC.
Split ADC-Based Calibration Technique:
In the split ADC structure, two same-pipelined ADCs work simultaneously. The final digital output is achieved by averaging the digitaloutput of two channels. Besides, their subtraction can be used in thecalibration process.
The method shifts the decision points of ADC in one of thechannels, called channel A, in comparison with their counterparts inchannelB. Thus, the transfer functions shown in Fig. 4 are produced.The channelBuses the original decision points of a 1.5-bit sub-ADC,i.e., ±0.25, while the other channel uses−0.125 and 0.375 decisionpoints. With these two transfer functions, five different regions arecreated. In the regionsi, iii,andv, these two transfer functions arethe same. Whereas, the regions ii and iv are the ones that can beused to extract the calibration coefficients with the LMS algorithmas follows:
Wheree(n)=Dout,A−Dout,Bandμ1andμ3are the update stepsizes of the first- and third-order coefficients, respectively. Moreover,Dres,Aand Dres,Bdenote the digital outputs of backend ADCs forthe stage under the calibration in channels AandB, respectively.
Figure 4: Stage’s transfer function of channelsAandBin the split structure
Proposed Calibration Technique:
In order to perform the digital background calibration, the structureof the proposed pipelined ADC has been improved to implement asingle channel split ADC. As depicted in Fig. 5, two extra comparators along with an interpolation filter are utilized to implement thedual-mode transfer function of the split pipelined ADC.
Here, unlike the conventional structure, the stage decision pointsare placed at−0.375 and 0.125, respectively. Two extra comparatorswith decision point’s at−0.125 and 0.375 are added to the stage inorder to perform the dual-mode transfer function. The main transfercurve relates to decision points of −0.375 and 0.125, while theauxiliary transfer curve is related to−0.125 and 0.375.
In the proposed calibration scheme, the difference between themain and auxiliary transfer curves in calibration regions,−0.375<Vin <−0.125 and 0.125 <Vin <0.375, are used to estimatethe calibration coefficients. This choice for decision points results intwice wider calibration regions in comparison Thus, the convergence time of the proposed calibration technique is decreased. Themain drawback of this choice is the limited offset voltage tolerancein the comparators.
Figure 5: Structure of the proposed calibration technique
The main transfer curve is considered for the normal operation ofthe pipelined ADC, while the auxiliary transfer curve is used in thecalibration process. The single channel split ADC structure for thecalibration is shown in Fig. 5. When the stage input sample is locatedin one of the calibration regions, a calibration cycle is done. In eachcalibration cycle, the stage is configured with the auxiliary transfercurve, while the main transfer curve is estimated with a 2Ltaps finiteimpulse response (FIR) interpolator. Indeed, the interpolator and twoextra comparators act like a virtual ADC to implement the proposedsingle channel split pipelined ADC.
Figure 6: Timing diagram of the proposed calibration scheme
The proposed calibration technique is performed adaptively andupdates the coefficients at each calibration cycle, which consists ofNinput samples. Timing diagram of the calibration process is shownin Fig. 6. In each calibration cycle, the ADC produces one samplebased on the auxiliary transfer curve, i.e., the desired sample in Fig. 6.When the desired sample is located in the one of calibration regions.
Advantages:
- Low power consumption
- Area coverage is low
Software implementation:
- Tanner tool