by nexgentech | Oct 24, 2017 | ieee project
FPGA Realization of Low Register SystolicAll-One-Polynomial Multipliers overGF(2m)and Their Applications inTrinomial Multipliers Abstract: Systolic all-one-polynomial (AOP) multipliers usually suffer from the problem of high register complexity, especially in...
by nexgentech | Oct 24, 2017 | ieee project
Adaptive Multibit Crosstalk-Aware Error Control Coding Scheme for On-Chip Communication Abstract: The presence of different noise sources and continuous increase in crosstalk in the deep sub micrometer technology raised concerns for on-chip communication reliability,...
by nexgentech | Oct 24, 2017 | ieee project
Hybrid Hardware/Software Floating-PointImplementations for Optimized Areaand Throughput Tradeoffs Abstract: Hybrid floating-point (FP) implementations improve software FP performance without incurring the area overhead of full hardware FP units. The proposed...
by nexgentech | Oct 24, 2017 | ieee project
ENFIRE: A Spatio-Temporal Fine-GrainedReconfigurable Hardware Abstract: Field programmable gate arrays (FPGAs) are well-established as fine-grained reconfigurable computing platforms. However, FPGAs demonstrate poor scalability in advanced technology nodes due to the...
by nexgentech | Oct 23, 2017 | ieee project
Hybrid LUTMultiplexer FPGA Logic Architectures Abstract: Hybrid configurable logic block architectures forfield-programmable gate arrays that contain a mixture of lookuptables and hardened multiplexers are evaluated toward the goalof higher logic density and area...
by nexgentech | Oct 23, 2017 | ieee project
Sign-Magnitude Encoding for Efficient VLSIRealization of Decimal Multiplication Abstract: Decimal X×Y multiplication is a complex operation, where intermediate partial products (IPPs) are commonly selected from a set of precomputed radix-10Xmultiples. Some works...
by nexgentech | Oct 23, 2017 | ieee project
Analysis and Design of a Low-Voltage Low-PowerDouble-Tail Comparator Abstract: The need for ultralow-power, area efficient and high speed analog-to-digital converters is pushing toward the use of dynamic regenerative comparators to maximize speed and power efficiency....
by nexgentech | Oct 23, 2017 | ieee project
High-Speed and Low-Latency ECC ProcessorImplementation Over GF(2m)on FPGA Abstract: In this paper, a novel high-speed elliptic curve cryptography (ECC) processor implementation for point multiplication (PM) on field-programmable gate array (FPGA) is proposed. A new...
by nexgentech | Oct 23, 2017 | ieee project
Sense Amplifier Half-Buffer (SAHB): A Low-PowerHigh-Performance AsynchronousLogic QDI Cell Template Abstract: We propose a novel asynchronous logic (async) quasi-delay-insensitive (QDI) sense-amplifier half-buffer (SAHB) cell design approach, with emphases on high...
by nexgentech | Oct 23, 2017 | ieee project
Efficient Designs of Multiported Memory on FPGA Abstract: The utilization of block RAMs (BRAMs) is a critical performance factor for multiported memory designs on field programmable gate arrays (FPGAs). Not only does the excessive demand on BRAMs block the usage of...
