by nexgentech | Oct 24, 2017 | ieee project
Interconnection Allocation between Functional Units and Registers in High-Level Synthesis Abstract: Data path interconnection on VLSI chips usually consumes a significant amount of both power and area. In this paper, we focus on the port assignment problem for binary...
by nexgentech | Oct 24, 2017 | ieee project
Delay Analysis for Current Mode Threshold Logic Gate Designs Abstract: Current mode is a popular CMOS-based implementation of threshold logic functions, where the gate delay depends on the sensor size. This paper presents a new implementation of current mode threshold...
by nexgentech | Oct 24, 2017 | ieee project
Low-Complexity Transformed Encoder Architectures for Quasi-Cyclic Non-binary LDPC Codes Over Subfields Abstract: Quasi-cyclic low-density parity-check (QC-LDPC) codes are adopted in many digital communication and storage systems. The encoding of these codes is...
by nexgentech | Oct 24, 2017 | ieee project
High-Throughput and Energy-Efficient Belief Propagation Polar Code Decoder Abstract: Owing to their capacity-achieving performance and low encoding and decoding complexity, polar codes have received significant attention recently. Successive cancellation decoding...
by nexgentech | Oct 24, 2017 | ieee project
Variation Resilient Power Sensor with an 80-ns Response Time for Fine-Grained Power Management Abstract: This paper presents real-time on-chip power and temperature sensors that provide fine-grained estimates for power consumption in systems-on-chip and also provide a...
by nexgentech | Oct 24, 2017 | ieee project
Temporarily Fine-Grained Sleep Technique for Near- and Subthreshold Parallel Architectures Abstract: This paper presents a design approach for improving energy-efficiency and throughput of parallel architectures in near- and subthreshold voltage circuits. The focus is...
