by nexgentech | Oct 24, 2017 | ieee project
A 5-Gb/s Digital Clock and Data Recovery Circuit with Reduced DCO Supply Noise Sensitivity Utilizing Coupling Network Abstract: A digital clock and data recovery (CDR) is presented, which employs a low supply sensitivity scheme for a digitally controlled oscillator...
by nexgentech | Oct 24, 2017 | ieee project
Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST Abstract: The generation of significant power droop (PD) during at-speed test performed by Logic Built-In Self Test (LBIST) is a serious concern for modern ICs. In fact, the PD originated during...
by nexgentech | Oct 24, 2017 | ieee project
Antiwear Leveling Design for SSDs With Hybrid ECC Capability Abstract: With the joint considerations of reliability and performance, hybrid error correction code (ECC) becomes an option in the designs of solid-state drives (SSDs). Unfortunately, wear leveling (WL)...
by nexgentech | Oct 24, 2017 | ieee project
A 100-mA, 99.11% Current Efficiency, 2-mVppRipple Digitally Controlled LDO with Active Ripple Suppression Abstract: Digital low-dropout (DLDO) regulators are gaining attention due to their design scalability for distributed multiple voltage domain applications...
by nexgentech | Oct 24, 2017 | ieee project
Area and Energy-Efficient Complementary Dual-Modular Redundancy Dynamic Memory for Space Applications Abstract: The limited size and power budgets of space-bound systems often contradict the requirements for reliable circuit operation within high-radiation...
by nexgentech | Oct 24, 2017 | ieee project
Probability-Driven Multibit Flip-Flop Integration With Clock Gating Abstract: Data-driven clock gated (DDCG) and multibit flip-flops (MBFFs) are two low-power design techniques that are usually treated separately. Combining these techniques into a single grouping...
