Variation Resilient Power Sensor with an 80-ns Response Time for Fine-Grained Power Management

Abstract:

This paper presents real-time on-chip power and temperature sensors that provide fine-grained estimates for power consumption in systems-on-chip and also provide a concurrent temperature estimate for dynamic power and temperature management. This sensor occupies an area of 0.01 mm 2in a 0.13-μm CMOS technology. With a simplified one-point calibration and a response time of 80 ns, it shows improvements in  input dynamic range by ten times, response time by six times, and sensitivity by three times over previous such sensors. A compact low-power current reference with a 3-σmaxTC of 127 ppm/°C and a line regulation of 1%/V is also presented, which is used in a replica-structure-based online calibration scheme, resulting in improved tolerance to variations in process, voltage, and temperature (PVT) and degradation due to supply noise as well as aging. The proposed architecture of this paper analysis the logic size, area and power consumption using Tanner tool.

Existing System:

As methods for direct online measurement of power have been unavailable, indirect methods such as performance counters or temperature sensors had to be used as proxies for estimating power. Hardware performance counters (HPCs) are sets of registers built into the microprocessor to count performance events such as instructions executed per cycle, data dependencies, or cache misses, whose outputs fit into linearized power models that are architecture dependent. Estimation accuracy also depends on the choice of counters, representative benchmarks used to formulate relationships between HPCs and actual power consumption. These representative expressions often vary according to architecture and the processor state (voltage and frequency). Process variations are also unaccounted in the HPCs unless these weights are recalculated for each processor state in each chip that takes significant testing overheads. These HPCs are only accurate in estimating power averaged over 10 000 or more cycles, whereas the errors in estimating dynamic power consumption can be as high as 40%. In addition, variation in on-chip temperatures can cause significant errors in the power values estimated from performance-counterbased models, and often an on-chip temperature sensor becomes essential for correcting these errors.

As a part of the power consumed is dissipated as heat, a rise in chip temperature can also be used as a proxy measure for estimating power consumption. The thermodynamics of this system is accurately modeled as a series of heat sources feeding into an RCnetwork. The rise and fall in temperatures therefore mimicRCcharging and discharging and can have time constants on the orders of milliseconds. This results in an inherent lag between occurrence of a power event and the availability of the information in the form of a temperature change. In addition, most reported temperature sensors have conversion times that vary from tens of microseconds to a few milliseconds. Hence, the overall system response time when using temperature sensors is very poor especially compared with microprocessors that run on sub-1-ns clock periods. Moving to multicore environments further complicates the annotation of temperature readings into power dissipation due to lateral spread of heat on the chip surface. Using software models to estimate power and to then convert these estimates into a 3-D thermal model has been studied. Techniques to improve the speed of convergence to a mathematical solution have also been explored. However, these methods still rely on indirect-software-based power estimates and are susceptible to ambient variations. Moreover, these techniques operate in time steps on the order of hundreds of milliseconds, which are at least six orders of magnitude too coarse

Separate digital dynamic power meters and temperature sensors have been implemented in multicore environments for fine-grained power management. However, separate circuits for temperature and power result in increased area overhead, and yet, the power meter accounts only for dynamic power and does not account for static power consumption. A current sensor described introduces a small resistance in series with the current path and samples the voltage drop across the resistor to estimate power accurately. However,  it has a poor temporal resolution (hertz to kilohertz) and a large area overhead (1 mm2). A sensor with a fast response time and a low area overhead was presented. However, the estimation required measurement of on-chip temperature, and even with a two-point calibration, estimates may be vulnerable to aging defects. It also has limited dynamic range, which although sufficient for the estimation of average power may not be sufficient to estimate spikes in power consumption. In addition, methods described equire an external current source for calibration, which increases the test complexity.

Disadvantages:

  • Power consumption is high

Proposed System:

Architecture:

Sensor with Replica Structure:

Power gating has become a necessary design technique to reduce the effect of ever-increasing leakage power on system performance. Large transistors known as sleep transistors are used to shut down voltage supply rails to inactive circuits. However, when the circuits are active, the virtual supply rails must be within tens of microvolts of Vdd and ground supply planes to ensure that the circuit performance does not degrade significantly. Hence, the sleep transistors operate in triode region with low VDS. In addition, decoupling capacitors (roughly ten times the switching capacitance of the circuit, BPC1 in Fig. 1) is also added as part of the power supply network to these virtual supply rails to reduce load regulation. As VDS across transistors operating in triode region is proportional to current flowing through them, we utilize this voltage drop to sense the current being drawn by the circuit under test (CUT).

Figure 1: Architecture of the power sensor

Fig. 1 shows the circuit schematic of the proposed power sensor, which includes a mechanism to recalibrate the estimated current according to ambient effects such as PVT variations, supply noise, and aging degradations. The basic structure of the sensor reported is retained. The sensor can be understood as a cascade of three blocks.

1) The sleep transistor M1 generates an inductive reactance (IR) drop that is proportional to the current flowing through it. 2) This voltage is converted into a current Ichg by a transconductance stage (Gm-stage), which consists of a source follower M3 followed by two source-degenerated common source stages (M5 and M9).

3) Current generated by this Gm-stage (drain current of M9) serves as the input to a current-controlled oscillator (CCO). In this design, the CCO consists of a capacitor Ca that is initially charged up to Vdd and slowly discharged by M9 at a rate ofIchg/Ca. When the voltage atCa reaches the inverter threshold voltage, its output flips, triggering a ripple through the delay chain, which is then used to quickly recharge the capacitor to Vdd by a strong transistor M11. The output at the end of delay line is used to drive a T-flip flop to generate a periodic waveform with 50% duty cycle whose frequency is directly proportional to the input current.

Advantages:

  • Power consumption is reduced

Software implementation:

  • Tanner tool