by nexgentech | Oct 23, 2017 | ieee project
High-Speed and Low-Latency ECC ProcessorImplementation Over GF(2m)on FPGA Abstract: In this paper, a novel high-speed elliptic curve cryptography (ECC) processor implementation for point multiplication (PM) on field-programmable gate array (FPGA) is proposed. A new...
by nexgentech | Oct 23, 2017 | ieee project
Sense Amplifier Half-Buffer (SAHB): A Low-PowerHigh-Performance AsynchronousLogic QDI Cell Template Abstract: We propose a novel asynchronous logic (async) quasi-delay-insensitive (QDI) sense-amplifier half-buffer (SAHB) cell design approach, with emphases on high...
by nexgentech | Oct 23, 2017 | ieee project
Efficient Designs of Multiported Memory on FPGA Abstract: The utilization of block RAMs (BRAMs) is a critical performance factor for multiported memory designs on field programmable gate arrays (FPGAs). Not only does the excessive demand on BRAMs block the usage of...
by nexgentech | Oct 23, 2017 | ieee project
Conditional-Boosting Flip-Flop for Near-Threshold Voltage Application Abstract: A conditional-boosting flip-flop is proposed for ultra-low voltage application where the supply voltage is scaled down to the near-threshold region. The proposed flip-flop adopts voltage...
by nexgentech | Oct 23, 2017 | ieee project
Low-Power Design for a Digit-Serial PolynomialBasis Finite Field Multiplier UsingFactoring Technique Abstract: In CMOS-based application-specific integrated circuit (ASIC) designs, total power consumption is dominated by dynamic power, where dynamic power consists of...
by nexgentech | Oct 23, 2017 | ieee project
Efficient Soft Cancelation Decoder Architecturesfor Polar Codes Abstract: The flooding belief propagation (FO-BP) and the soft-cancelation (SCAN) algorithms are the two most popular soft-output BP algorithms for the decoding of capacity-achieving polar codes. The...
