by nexgentech | Oct 24, 2017 | ieee project
Hardware-Efficient Built-In Redundancy Analysis for Memory with Various Spares Abstract: Memory capacity continues to increase, and many semiconductor manufacturing companies are trying to stack memory dice for larger memory capacities. Therefore, built-in redundancy...
by nexgentech | Oct 24, 2017 | ieee project
Resource-Efficient SRAM-based Ternary Content Addressable Memory Abstract: Static random access memory (SRAM)-based ternary content addressable memory (TCAM) offers TCAM functionality by emulating it with SRAM. However, this emulation suffers from reduced memory...
by nexgentech | Oct 24, 2017 | ieee project
On Micro-architectural Mechanisms for Cache Wear out Reduction Abstract: Hot carrier injection (HCI) and bias temperature instability (BTI) are two of the main deleterious effects that increase a transistor’s threshold voltage over the lifetime of a microprocessor....
by nexgentech | Oct 24, 2017 | ieee project
Write-Amount-Aware Management Policies for STT-RAM Caches Abstract: Spin-transfer torque random access memory (STT-RAM) technology has emerged as one of the most promising memory technologies owing to its non-volatility, high density, and low-leakage power...
by nexgentech | Oct 24, 2017 | ieee project
Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding Abstract: A new low-power (LP) scan-based built-in self-test (BIST) technique is proposed based on weighted pseudorandom test pattern generation and reseeding....
by nexgentech | Oct 24, 2017 | ieee project
A 2.4–3.6-GHz Wideband Sub-harmonically Injection-Locked PLL with Adaptive Injection Timing Alignment Technique Abstract: This paper proposes a wideband subharmonically injection-locked PLL (SILPLL) with adaptive injection timing alignment technique. The SILPLL...
