by nexgentech | Oct 24, 2017 | ieee project
Adaptive Multibit Crosstalk-Aware Error Control Coding Scheme for On-Chip Communication Abstract: The presence of different noise sources and continuous increase in crosstalk in the deep sub micrometer technology raised concerns for on-chip communication reliability,...
by nexgentech | Oct 24, 2017 | ieee project
Hybrid Hardware/Software Floating-PointImplementations for Optimized Areaand Throughput Tradeoffs Abstract: Hybrid floating-point (FP) implementations improve software FP performance without incurring the area overhead of full hardware FP units. The proposed...
by nexgentech | Oct 24, 2017 | ieee project
ENFIRE: A Spatio-Temporal Fine-GrainedReconfigurable Hardware Abstract: Field programmable gate arrays (FPGAs) are well-established as fine-grained reconfigurable computing platforms. However, FPGAs demonstrate poor scalability in advanced technology nodes due to the...
by nexgentech | Oct 23, 2017 | ieee project
Hybrid LUTMultiplexer FPGA Logic Architectures Abstract: Hybrid configurable logic block architectures forfield-programmable gate arrays that contain a mixture of lookuptables and hardened multiplexers are evaluated toward the goalof higher logic density and area...
by nexgentech | Oct 23, 2017 | ieee project
Sign-Magnitude Encoding for Efficient VLSIRealization of Decimal Multiplication Abstract: Decimal X×Y multiplication is a complex operation, where intermediate partial products (IPPs) are commonly selected from a set of precomputed radix-10Xmultiples. Some works...
by nexgentech | Oct 23, 2017 | ieee project
Analysis and Design of a Low-Voltage Low-PowerDouble-Tail Comparator Abstract: The need for ultralow-power, area efficient and high speed analog-to-digital converters is pushing toward the use of dynamic regenerative comparators to maximize speed and power efficiency....
