by nexgentech | Oct 24, 2017 | ieee project
Energy-Efficient VLSI Realization of Binary64 Division with Redundant Number Systems Abstract: VLSI realizations of digit-recurrence binary division usually use redundant representation of partial remainders and quotient digits. The former allows for fast carry-free...
by nexgentech | Oct 24, 2017 | ieee project
A 92-dB DR, 24.3-mW, 1.25-MHz BW Sigma–Delta Modulator Using Dynamically Biased Op Amp Sharing Abstract: A 2–2 cascaded switched-capacitor sigma-delta modulator is presented for design of low-voltage, low-power, broadband analog-to-digital conversion. To reduce power...
by nexgentech | Oct 24, 2017 | ieee project
A 0.1–2-GHz Quadrature Correction Loop for Digital Multiphase Clock Generation Circuits in 130-nm CMOS Abstract: A 100-MHz–2-GHz closed-loop analog in-phase/quadrature correction circuit for digital clocks is presented. The proposed circuit consists of a phase-locked...
by nexgentech | Oct 24, 2017 | ieee project
A Single Channel Split ADC Structure for Digital Background Calibration in Pipelined ADCs Abstract: A digital background calibration technique based on the concept of split analog-to-digital converter (ADC) structure is proposed for pipelined ADCs to correct the gain...
by nexgentech | Oct 24, 2017 | ieee project
Energy-Efficient TCAM Search Engine Design Using Priority-Decision in Memory Technology Abstract: Ternary content-addressable memory (TCAM)-based search engines generally need a priority encoder (PE) to select the highest priority match entry for resolving the...
by nexgentech | Oct 24, 2017 | ieee project
COMEDI: Combinatorial Election of Diagnostic Vectors From Detection Test Sets for Logic Circuits Abstract: Although the modern automatic test pattern generation (ATPG) tools can efficiently produce near-optimal test sets with high fault-coverage for a...
by nexgentech | Oct 24, 2017 | ieee project
Publicly Verifiable Watermarking for Intellectual Property Protection in FPGA Design Abstract: Watermarking as a novel intellectual property (IP) protection technique can protect field-programmable gate array IPs from infringement. However, existing watermarking...
by nexgentech | Oct 24, 2017 | ieee project
A 0.45 V 147–375 nW ECG Compression ProcessorWith Wavelet Shrinkage and AdaptiveTemporal Decimation Architectures Abstract: This paper presents a real-time electrocardiogram (ECG) data compression processor with improved energy efficiency while maintaining high...
by nexgentech | Oct 24, 2017 | ieee project
10T SRAM Using Half-VDDPrecharge andRow-Wise Dynamically Powered ReadPort for Low Switching Powerand Ultralow RBL Leakage Abstract: We present, in this paper, a new 10T static random access memory cell having single ended decoupled read-bitline (RBL) with a 4T read...
by nexgentech | Oct 24, 2017 | ieee project
An On-Chip Monitoring Circuit for Signal-IntegrityAnalysis of 8-Gb/s Chip-to-Chip Interfaces WithSource-Synchronous Clock Abstract: This paper presents an on-chip monitoring circuit (OCMC) for analyzing the signal integrity of high speed signals for a chip-to-chip...
