by nexgentech | Oct 24, 2017 | ieee project
A Fault Tolerance Technique for Combinational Circuits Based on Selective-Transistor Redundancy Abstract: With fabrication technology reaching nano-levels, systems are becoming more prone to manufacturing defects with higher susceptibility to soft errors. This paper...
by nexgentech | Oct 24, 2017 | ieee project
Soft Error Rate Reduction of Combinational Circuits Using Gate Sizing in the Presence of Process Variations Abstract: Soft errors in combinational logic circuits are emerging as a significant reliability concern for nanoscale VLSI designs. This paper presents a novel...
by nexgentech | Oct 24, 2017 | ieee project
High-Speed Parallel LFSR Architectures Based on Improved State-Space Transformations Abstract: Linear feedback shift register (LFSR) has been widely applied in BCH and CRC encoding. In order to increase the system throughput, the parallelization of LFSR is usually...
by nexgentech | Oct 24, 2017 | ieee project
A High-Speed and Power-Efficient Voltage Level Shifter for Dual-Supply Applications Abstract: This brief presents a fast and power-efficient voltage level shifting circuit capable of converting extremely low levels of input voltages into high output voltage levels....
by nexgentech | Oct 24, 2017 | ieee project
A 5-Gb/s Digital Clock and Data Recovery Circuit with Reduced DCO Supply Noise Sensitivity Utilizing Coupling Network Abstract: A digital clock and data recovery (CDR) is presented, which employs a low supply sensitivity scheme for a digitally controlled oscillator...
by nexgentech | Oct 24, 2017 | ieee project
Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST Abstract: The generation of significant power droop (PD) during at-speed test performed by Logic Built-In Self Test (LBIST) is a serious concern for modern ICs. In fact, the PD originated during...
by nexgentech | Oct 24, 2017 | ieee project
Antiwear Leveling Design for SSDs With Hybrid ECC Capability Abstract: With the joint considerations of reliability and performance, hybrid error correction code (ECC) becomes an option in the designs of solid-state drives (SSDs). Unfortunately, wear leveling (WL)...
by nexgentech | Oct 24, 2017 | ieee project
A 100-mA, 99.11% Current Efficiency, 2-mVppRipple Digitally Controlled LDO with Active Ripple Suppression Abstract: Digital low-dropout (DLDO) regulators are gaining attention due to their design scalability for distributed multiple voltage domain applications...
by nexgentech | Oct 24, 2017 | ieee project
Area and Energy-Efficient Complementary Dual-Modular Redundancy Dynamic Memory for Space Applications Abstract: The limited size and power budgets of space-bound systems often contradict the requirements for reliable circuit operation within high-radiation...
by nexgentech | Oct 24, 2017 | ieee project
Probability-Driven Multibit Flip-Flop Integration With Clock Gating Abstract: Data-driven clock gated (DDCG) and multibit flip-flops (MBFFs) are two low-power design techniques that are usually treated separately. Combining these techniques into a single grouping...
