by nexgentech | Oct 24, 2017 | ieee project
Dual-Quality 4:2 Compressors for Utilizing inDynamic Accuracy Configurable Multipliers Abstract: In this paper, we propose four 4:2 compressors, which have the flexibility of switching between the exact and approximate operating modes. In the approximate mode, these...
by nexgentech | Oct 24, 2017 | ieee project
FPGA Realization of Low Register SystolicAll-One-Polynomial Multipliers overGF(2m)and Their Applications inTrinomial Multipliers Abstract: Systolic all-one-polynomial (AOP) multipliers usually suffer from the problem of high register complexity, especially in...
by nexgentech | Oct 24, 2017 | ieee project
Adaptive Multibit Crosstalk-Aware Error Control Coding Scheme for On-Chip Communication Abstract: The presence of different noise sources and continuous increase in crosstalk in the deep sub micrometer technology raised concerns for on-chip communication reliability,...
by nexgentech | Oct 24, 2017 | ieee project
Hybrid Hardware/Software Floating-PointImplementations for Optimized Areaand Throughput Tradeoffs Abstract: Hybrid floating-point (FP) implementations improve software FP performance without incurring the area overhead of full hardware FP units. The proposed...
by nexgentech | Oct 24, 2017 | ieee project
ENFIRE: A Spatio-Temporal Fine-GrainedReconfigurable Hardware Abstract: Field programmable gate arrays (FPGAs) are well-established as fine-grained reconfigurable computing platforms. However, FPGAs demonstrate poor scalability in advanced technology nodes due to the...
by nexgentech | Oct 23, 2017 | ieee project
Hybrid LUTMultiplexer FPGA Logic Architectures Abstract: Hybrid configurable logic block architectures forfield-programmable gate arrays that contain a mixture of lookuptables and hardened multiplexers are evaluated toward the goalof higher logic density and area...
