by nexgentech | Oct 24, 2017 | ieee project
A 0.1–2-GHz Quadrature Correction Loop for Digital Multiphase Clock Generation Circuits in 130-nm CMOS Abstract: A 100-MHz–2-GHz closed-loop analog in-phase/quadrature correction circuit for digital clocks is presented. The proposed circuit consists of a phase-locked...
by nexgentech | Oct 24, 2017 | ieee project
A Single Channel Split ADC Structure for Digital Background Calibration in Pipelined ADCs Abstract: A digital background calibration technique based on the concept of split analog-to-digital converter (ADC) structure is proposed for pipelined ADCs to correct the gain...
by nexgentech | Oct 24, 2017 | ieee project
Energy-Efficient TCAM Search Engine Design Using Priority-Decision in Memory Technology Abstract: Ternary content-addressable memory (TCAM)-based search engines generally need a priority encoder (PE) to select the highest priority match entry for resolving the...
by nexgentech | Oct 24, 2017 | ieee project
COMEDI: Combinatorial Election of Diagnostic Vectors From Detection Test Sets for Logic Circuits Abstract: Although the modern automatic test pattern generation (ATPG) tools can efficiently produce near-optimal test sets with high fault-coverage for a...
by nexgentech | Oct 24, 2017 | ieee project
Publicly Verifiable Watermarking for Intellectual Property Protection in FPGA Design Abstract: Watermarking as a novel intellectual property (IP) protection technique can protect field-programmable gate array IPs from infringement. However, existing watermarking...
by nexgentech | Oct 24, 2017 | ieee project
A 0.45 V 147–375 nW ECG Compression ProcessorWith Wavelet Shrinkage and AdaptiveTemporal Decimation Architectures Abstract: This paper presents a real-time electrocardiogram (ECG) data compression processor with improved energy efficiency while maintaining high...
