by nexgentech | Oct 24, 2017 | ieee project
Temporarily Fine-Grained Sleep Technique for Near- and Subthreshold Parallel Architectures Abstract: This paper presents a design approach for improving energy-efficiency and throughput of parallel architectures in near- and subthreshold voltage circuits. The focus is...
by nexgentech | Oct 24, 2017 | ieee project
A High-Efficiency 6.78-MHz Full Active Rectifier with Adaptive Time Delay Control for Wireless Power Transmission Abstract: This paper presents a full active rectifier consisting of GaN devices and a CMOS controller designed for wireless power transmission in...
by nexgentech | Oct 24, 2017 | ieee project
Fault Diagnosis Schemes for Low-Energy Block Cipher Midori Benchmarked on FPGA BULK IEEE VLSI PROJECTS Abstract: Achieving secure high-performance implementations for constrained applications such as implantable and wearable medical devices are a priority in efficient...
by nexgentech | Oct 24, 2017 | ieee project
A 65-nm CMOS Constant Current Source with Reduced PVT Variation Abstract: This paper presents a new nanometer-based low-power constant current reference that attains a small value in the total process–voltage–temperature variation. The circuit architecture is based on...
by nexgentech | Oct 24, 2017 | ieee project
Fast Automatic Frequency Calibrator Using an Adaptive Frequency Search Algorithm Abstract: A new adaptive frequency search algorithm (A-FSA) is presented for a fast automatic frequency calibrator in wideband phase-locked loops (PLLs). The proposed A-FSA optimizes the...
by nexgentech | Oct 24, 2017 | ieee project
An FPGA-Based Hardware Accelerator for Traffic Sign Detection Abstract: Traffic sign detection plays an important role in a number of practical applications, such as intelligent driver assistance and roadway inventory management. In order to process the large amount...
by nexgentech | Oct 24, 2017 | ieee project
Reordering Tests for Efficient Fail Data Collection and Tester Time Reduction Abstract: During fail data collection, a tester collects information that is useful for defect diagnosis. If fail data collection can be terminated early, the tester time as well as the...
by nexgentech | Oct 24, 2017 | ieee project
A Way-Filtering-Based Dynamic Logical–Associative Cache Architecture for Low-Energy Consumption Abstract: Last-level caches (LLCs) help improve performance but suffer from energy overhead because of their large sizes. An effective solution to this problem is to...
by nexgentech | Oct 24, 2017 | ieee project
Hardware-Efficient Built-In Redundancy Analysis for Memory with Various Spares Abstract: Memory capacity continues to increase, and many semiconductor manufacturing companies are trying to stack memory dice for larger memory capacities. Therefore, built-in redundancy...
by nexgentech | Oct 24, 2017 | ieee project
Resource-Efficient SRAM-based Ternary Content Addressable Memory Abstract: Static random access memory (SRAM)-based ternary content addressable memory (TCAM) offers TCAM functionality by emulating it with SRAM. However, this emulation suffers from reduced memory...
