by nexgentech | Oct 25, 2017 | ieee project
A NEW SERVICE MECHANISM FOR PROFITOPTIMIZATIONS OF A CLOUD PROVIDER AND ITS USERS ABSTRACT In this paper, we try to design a service mechanism for profit optimizations of both a cloud provider and its multiple users.Weconsider the problem from a game theoretic...
by nexgentech | Oct 25, 2017 | ieee project
A CROSS TENANT ACCESS CONTROL (CTAC) MODEL FOR CLOUD COMPUTING: FORMAL SPECIFICATION AND VERIFICATION ABSTRACT Sharing of resources on the cloud can be achievedon a large scale since it is cost effective and location independent.Despite the hype surrounding cloud...
by nexgentech | Oct 25, 2017 | ieee project
APPLICATION-AWARE BIG DATA DEDUPLICATION IN CLOUD ENVIRONMENT ABSTRACT Deduplication has become a widely deployed technology in cloud data centers to improve IT resources efficiency. However, traditional techniques face a great challenge in big data deduplication to...
by nexgentech | Oct 24, 2017 | ieee project
Stochastic Implementation and Analysis of Dynamical Systems Similar to the Logistic Map Abstract: Stochastic computing (SC) is a digital computation approach that operates on random bit streams to perform complex tasks with much smaller hardware footprints compared...
by nexgentech | Oct 24, 2017 | ieee project
Multicast-Aware High-Performance Wireless Network-on-Chip Architectures Abstract: Today’s multiprocessor platforms employ the network-on-chip (NoC) architecture as the preferable communication backbone. Conventional NoCs are designed predominantly for unicast data...
by nexgentech | Oct 24, 2017 | ieee project
A Fault Tolerance Technique for Combinational Circuits Based on Selective-Transistor Redundancy Abstract: With fabrication technology reaching nano-levels, systems are becoming more prone to manufacturing defects with higher susceptibility to soft errors. This paper...
by nexgentech | Oct 24, 2017 | ieee project
Soft Error Rate Reduction of Combinational Circuits Using Gate Sizing in the Presence of Process Variations Abstract: Soft errors in combinational logic circuits are emerging as a significant reliability concern for nanoscale VLSI designs. This paper presents a novel...
by nexgentech | Oct 24, 2017 | ieee project
High-Speed Parallel LFSR Architectures Based on Improved State-Space Transformations Abstract: Linear feedback shift register (LFSR) has been widely applied in BCH and CRC encoding. In order to increase the system throughput, the parallelization of LFSR is usually...
by nexgentech | Oct 24, 2017 | ieee project
A High-Speed and Power-Efficient Voltage Level Shifter for Dual-Supply Applications Abstract: This brief presents a fast and power-efficient voltage level shifting circuit capable of converting extremely low levels of input voltages into high output voltage levels....
by nexgentech | Oct 24, 2017 | ieee project
A 5-Gb/s Digital Clock and Data Recovery Circuit with Reduced DCO Supply Noise Sensitivity Utilizing Coupling Network Abstract: A digital clock and data recovery (CDR) is presented, which employs a low supply sensitivity scheme for a digitally controlled oscillator...
