A 5-Gb/s Digital Clock and Data Recovery Circuit with Reduced DCO Supply Noise Sensitivity Utilizing Coupling Network

Abstract:

A digital clock and data recovery (CDR) is presented, which employs a low supply sensitivity scheme for a digitally controlled oscillator (DCO). A coupling network comprising capacitors, resistors, and coupling buffers enhances the supply variation immunity of the DCO and mitigates the jitter performance degradation. A supply variationdependent bias generator produces the corresponding bias voltage to alleviate the supply variation with minimal area and power penalty. The proposed scheme improves 29.3 ps of peak-to-peak jitter and 11.5 Db of spur level, at 6 and 5 MHz 50 mVpp sinusoidal supply noise tone, respectively. Fabricated in a 65-nm CMOS process, the proposed CDR operates at 5-Gb/s data rate with BER <10 −12 for PRBS 31 and consumes 15.4 mW. The CDR occupies an active die area of 0.075 mm2. The proposed architecture of this paper analysis the logic size, area and power consumption using Tanner tool.

Existing System:

As technology advances, mixed-signal integrated systems gain popularity due to area efficiency, scalability, and portability of digital circuits. This trend necessitates wide use of digital clock and data recovery (CDR) circuits in high-speed serial links. Several fully integrated digital CDRs have been published. While a digital CDR mainly focuses on enhancing the jitter performance from jittery input data, it is required to consider power supply variation for the reliable operation of the CDR. The integration of the digital circuits has caused supply noise to become the principal noise constraint on the oscillator performance.

Figure 1: Conventional digital CDR. (a) Block diagram with DCO supply noise. (b) Timing waveform without supply noise and with supply noise

Fig. 1(a) shows a conventional digital CDR consisting of a digital phase detector, a digital loop filter (DLF), and a digitally controlled oscillator (DCO). Fig. 1(b) shows an impact with supply noise on the DCO. Compared with the DCO without the supply noise, the clock jitter (tCK) is increased due to the jitter accumulation characteristic, and as a result, the sampling margin is severely reduced. Without a supply noise reduction technique, a CDR cannot provide good jitter performance with enough noise margin. A voltage regulator has been employed on the oscillator to mitigate supply noise. The regulator prevents the DCO from suffering from the supply variation. However, it requires the wider regulator bandwidth compared with that of the CDR in order not to degrade the CDR performance at the expense of power consumption. Furthermore, the bulky output capacitor of the regulator suffers from the large area, and high drop-out voltage leads to high supply voltage. Supply noise compensation schemes have been used to achieve supply noise tolerance at a cost of additional complex calibration. A resistor desensitizing DCO from supply noise has been presented in phase-locked loop at the cost of higher power consumption for given frequency.

Disadvantages:

  • Power consumption is high

 

Proposed System:

We propose the compensation approach with a coupling network comprising of capacitors, resistors, and coupling buffers (CBs) with a supply variation-dependent bias generator (SDBG) to compensate for supply noise and enhance the reliability of the CDR with low power and area penalty.

Figure 2: Conceptual block diagram of the oscillator

Concept of supply insensitive oscillator:

Fig. 2 shows a conceptual block diagram of the ring oscillator. Differential CMOS inverters are typically used in the ring based oscillator due to multiphase generation and common-mode noise rejection. A delay cell consists of a pair of main inverter, cross-coupled inverters, and a supply noise compensation unit. The characteristics of the supply induced frequency variation are also shown in Fig. 2. The frequency drifts with regard to the supply variation are denoted as KMI and KXC for the main and cross coupled inverter pairs, respectively. The drive strength difference between the inverters causes the conventional DCO to have poor supply sensitivity, resulting in jitter increase. Furthermore, the jitter accumulation causes the system to have worse jitter performance. Therefore, this brief introduces a supply variation compensation unit which is added to the each delay cell.KSC that represents the negative frequency drift of the compensation unit is controlled by the SDBG. The compensation unit alleviates the supply induced frequency variation and reduces the output jitter.

Proposed CDR architecture:

Fig. 3 shows the building blocks of the proposed digital CDR. The CDR consists of a half-rate BBPD, a DLF, a DCO compensated for supply variation, and an SDBG. The BBPD generates UP/DN pulses, which represent the binary phase difference between DIN and CKREC. The UP/DN pulses drive a proportional and an integral paths with gains of KP and KI , respectively. In the proportional path, the logic gates and an UP/DN serializer are used to control KP. In the integral path, a decimator allows easy implementation of following fully synthesized digital circuits in the integral path.

Figure 3: Proposed digital CDR

The frequency of CKRECis first reduced by A, and then, the result is divided by M. This cascaded approach of the decimator allows the time-dithered delta–sigma modulator (TDDSM) to be performed with a variable sampling period. The accumulator output is directed in parallel paths to the TDDSM. Since the LSBs contain useful phase information, some LSBs and MSBs are employed in the TDDSM to enhance the jitter performance. This approach eliminates the need of additional accumulator bits and reduces hardware complexity.

Supply Variation-Dependent Bias Generator:

The SDBG is used to generateVOUTin proportion to the supply voltage variation. Fig. 4(a) shows the schematic of the SDBG, which consists of a supply voltage divider, a common gate (CG) amplifier, and a common source (CS) amplifier.

Figure 4: SDBG. (a) Schematic. (b) Time-domain waveform of the supply with noise. (c) Timing waveform of the SDBG

DCO Compensated for Supply Variation Utilizing Coupling Network:

Fig. 5 shows the schematic of the DCO compensated for supply variation. The DCO that is based on four stages of pseudo differential inverters generates in-phase (CK I) and quadrature (CKQ) clocks for the half-rate BBPD. In the proportional path, a serialized UP/DN pulse alters the internal DCO supply [4]. The DCO frequency is given by 32-bit integral word with the varactor loads (CAP BANK) in the integral path. The delay cell is composed of a pair of main inverters (MAIN), a pair of cross-coupled inverters (XC), and a coupling network with capacitors, resistors, and CBs.

Figure 5: Schematic of the DCO

Advantages:

  • Better performance
  • Power reduction

Software implementation:

  • Tanner tool