by nexgentech | Oct 24, 2017 | ieee project
Scalable Device Array for StatisticalCharacterization of BTI-Related Parameters Abstract: A device array circuit, scalable in terms of the number of transistors used, is proposed. The proposed array facilitates accurate and simultaneous bias voltage application to a...
by nexgentech | Oct 24, 2017 | ieee project
A Single Channel Split ADC Structure for DigitalBackground Calibration in Pipelined ADCs Abstract: A digital background calibration technique based on the concept of split analog-to-digital converter (ADC) structure is proposed for pipelined ADCs to correct the gain...
by nexgentech | Oct 24, 2017 | ieee project
A 2.5-ps Bin Size and 6.7-ps ResolutionFPGA Time-to-Digital Converter Basedon Delay Wrapping and Averaging Abstract: A high-resolution time-to-digital converter (TDC) implemented with field programmable gate array (FPGA) based on delay wrapping and averaging is...
by nexgentech | Oct 24, 2017 | ieee project
Coordinate Rotation-Based Low ComplexityK-Means Clustering Architecture Abstract: In this brief, we propose a low-complexity architectural implementation of the K-means-based clustering algorithm used widely in mobile health monitoring applications for unsupervised...
by nexgentech | Oct 24, 2017 | ieee project
Dual-Quality 4:2 Compressors for Utilizing inDynamic Accuracy Configurable Multipliers Abstract: In this paper, we propose four 4:2 compressors, which have the flexibility of switching between the exact and approximate operating modes. In the approximate mode, these...
by nexgentech | Oct 24, 2017 | ieee project
FPGA Realization of Low Register SystolicAll-One-Polynomial Multipliers overGF(2m)and Their Applications inTrinomial Multipliers Abstract: Systolic all-one-polynomial (AOP) multipliers usually suffer from the problem of high register complexity, especially in...
by nexgentech | Oct 24, 2017 | ieee project
Adaptive Multibit Crosstalk-Aware Error Control Coding Scheme for On-Chip Communication Abstract: The presence of different noise sources and continuous increase in crosstalk in the deep sub micrometer technology raised concerns for on-chip communication reliability,...
by nexgentech | Oct 24, 2017 | ieee project
Hybrid Hardware/Software Floating-PointImplementations for Optimized Areaand Throughput Tradeoffs Abstract: Hybrid floating-point (FP) implementations improve software FP performance without incurring the area overhead of full hardware FP units. The proposed...
by nexgentech | Oct 24, 2017 | ieee project
ENFIRE: A Spatio-Temporal Fine-GrainedReconfigurable Hardware Abstract: Field programmable gate arrays (FPGAs) are well-established as fine-grained reconfigurable computing platforms. However, FPGAs demonstrate poor scalability in advanced technology nodes due to the...
by nexgentech | Oct 23, 2017 | ieee project
Hybrid LUTMultiplexer FPGA Logic Architectures Abstract: Hybrid configurable logic block architectures forfield-programmable gate arrays that contain a mixture of lookuptables and hardened multiplexers are evaluated toward the goalof higher logic density and area...
