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Interconnection Allocation between Functional Units and Registers in High-Level Synthesis

by nexgentech | Oct 24, 2017 | ieee project

Interconnection Allocation between Functional Units and Registers in High-Level Synthesis Abstract: Data path interconnection on VLSI chips usually consumes a significant amount of both power and area. In this paper, we focus on the port assignment problem for binary...

Delay Analysis for Current Mode Threshold Logic Gate Designs

by nexgentech | Oct 24, 2017 | ieee project

Delay Analysis for Current Mode Threshold Logic Gate Designs Abstract: Current mode is a popular CMOS-based implementation of threshold logic functions, where the gate delay depends on the sensor size. This paper presents a new implementation of current mode threshold...

Low-Complexity Transformed Encoder Architectures for Quasi-Cyclic Non-binary LDPC Codes Over Subfields

by nexgentech | Oct 24, 2017 | ieee project

Low-Complexity Transformed Encoder Architectures for Quasi-Cyclic Non-binary LDPC Codes Over Subfields Abstract: Quasi-cyclic low-density parity-check (QC-LDPC) codes are adopted in many digital communication and storage systems. The encoding of these codes is...

High-Throughput and Energy-Efficient Belief Propagation Polar Code Decoder

by nexgentech | Oct 24, 2017 | ieee project

High-Throughput and Energy-Efficient Belief Propagation Polar Code Decoder Abstract: Owing to their capacity-achieving performance and low encoding and decoding complexity, polar codes have received significant attention recently. Successive cancellation decoding...

Variation Resilient Power Sensor with an 80-ns Response Time for Fine-Grained Power Management

by nexgentech | Oct 24, 2017 | ieee project

Variation Resilient Power Sensor with an 80-ns Response Time for Fine-Grained Power Management Abstract: This paper presents real-time on-chip power and temperature sensors that provide fine-grained estimates for power consumption in systems-on-chip and also provide a...

Temporarily Fine-Grained Sleep Technique for Near- and Subthreshold Parallel Architectures

by nexgentech | Oct 24, 2017 | ieee project

Temporarily Fine-Grained Sleep Technique for Near- and Subthreshold Parallel Architectures Abstract: This paper presents a design approach for improving energy-efficiency and throughput of parallel architectures in near- and subthreshold voltage circuits. The focus is...

A High-Efficiency 6.78-MHz Full Active Rectifier with Adaptive Time Delay Control for Wireless Power Transmission

by nexgentech | Oct 24, 2017 | ieee project

A High-Efficiency 6.78-MHz Full Active Rectifier with Adaptive Time Delay Control for Wireless Power Transmission Abstract: This paper presents a full active rectifier consisting of GaN devices and a CMOS controller designed for wireless power transmission in...

Fault Diagnosis Schemes for Low-Energy Block Cipher Midori Benchmarked on FPGA

by nexgentech | Oct 24, 2017 | ieee project

Fault Diagnosis Schemes for Low-Energy Block Cipher Midori Benchmarked on FPGA BULK IEEE VLSI PROJECTS Abstract: Achieving secure high-performance implementations for constrained applications such as implantable and wearable medical devices are a priority in efficient...

A 65-nm CMOS Constant Current Source with Reduced PVT Variation

by nexgentech | Oct 24, 2017 | ieee project

A 65-nm CMOS Constant Current Source with Reduced PVT Variation Abstract: This paper presents a new nanometer-based low-power constant current reference that attains a small value in the total process–voltage–temperature variation. The circuit architecture is based on...

Fast Automatic Frequency Calibrator Using an Adaptive Frequency Search Algorithm

by nexgentech | Oct 24, 2017 | ieee project

Fast Automatic Frequency Calibrator Using an Adaptive Frequency Search Algorithm Abstract: A new adaptive frequency search algorithm (A-FSA) is presented for a fast automatic frequency calibrator in wideband phase-locked loops (PLLs). The proposed A-FSA optimizes the...
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