| 1. |
A 0.521 V Fast Lock-In Adpll For Supporting Dynamic Voltage And Frequency Scaling |
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| 2. |
A 3-D Cpu-Fpga-Dram Hybrid Architecture For Low-Power Computation |
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| 3. |
A 520k (18 900, 17 010) Array Dispersion Ldpc Decoder Architectures For Nand-Flash Memory |
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| 4. |
A Cellular Network Architecture With Polynomial Weight Functions |
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| 5. |
A Configurable Parallel Hardware Architecture For Efficient Integral Histogram Image Computing |
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| 6. |
A Dynamically Reconfigurable Multi-Asip Architecture For Multistandard And Multimode Turbo Decoding |
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| 7. |
A Fast Fault-Tolerant Architecture For Sauvola Local Image Thresholding Algorithm Using Stochastic Computing |
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| 8. |
A Fast-Acquisition All-Digital Delay-Locked Loop Using A Starting-Bit Prediction Algorithm For The Successive-Approximation Register |
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| 9. |
A Fast-Transient Wide-Voltage-Range Digital-Controlled Buck Converter With Cycle-Controlled Dpwm |
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| 10. |
A Fully Digital Front-End Architecture For Ecg Acquisition System With 0.5 V Supply |
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| 11. |
A High Throughput List Decoder Architecture For Polar Codes |
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| 12. |
A High-Performance Fir Filter Architecture For Fixed And Reconfigurable Applications |
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| 13. |
A High-Speed Fpga Implementation Of An Rsd-Based Ecc Processor |
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| 14. |
A High-Throughput Hardware Design Of A One-Dimensional Spiht Algorithm |
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| 15. |
A Low-Power Broad-Bandwidth Noise Cancellation Vlsi Circuit Design For In-Ear Headphones |
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| 16. |
A Mixed-Decimation Mdf Architecture For Radix-2k Parallel Fft |
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| 17. |
A New Binary-Halved Clustering Method And Ert Processor For Assr System |
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| 18. |
A New Cdma Encodingdecoding Method For On-Chip Communication Network |
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| 19. |
A New Optimal Algorithm For Energy Saving In Embedded System With Multiple Sleep Modes |
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| 20. |
A New Parallel Vlsi Architecture For Real-Time Electrical Capacitance Tomography |
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| 21. |
A Normal Io Order Radix-2 Fft Architecture To Process Twin Data Streams For Mimo |
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| 22. |
A Novel Quantum-Dot Cellular Automata X-Bit X 32-Bit Sram |
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| 23. |
A Performance Degradation Tolerable Cache Design By Exploiting Memory Hierarchies |
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| 24. |
A Single-Stage Low-Dropout Regulator With A Wide Dynamic Range For Generic Applications |
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| 25. |
A Systematic Design Methodology Of Asynchronous Sar Adcs |
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| 26. |
Algorithm And Architecture Of Configurable Joint Detection And Decoding For Mimo Wireless Communications With Convolution Codes |
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| 27. |
An Add-On Type Real-Time Jitter Tolerance Enhancer For Digital Communication Receivers |
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| 28. |
An All-Digital Approach To Supply Noise Cancellation In Digital Phase-Locked Loop |
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| 29. |
An Efficient Single And Double-Adjacent Error Correcting Parallel Decoder For The (24,12) Extended Golay Code |
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| 30. |
Area-Aware Cache Update Trackers For Postsilicon Validation |
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| 31. |
Argo A Real-Time Network-On-Chip Architecture With An Efficient Gals Implementation |
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| 32. |
Code Compression For Embedded Systems Using Separated Dictionaries |
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| 33. |
Concept, Design, And Implementation Of Reconfigurable Cordic |
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| 34. |
Design And Fpga Implementation Of A Reconfigurable 1024-Channel Channelization Architecture For Sdr Application |
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| 35. |
Design And Implementation Of High-Speed All-Pass Transformation-Based Variable |
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| 36. |
Digital Filters By Breaking The Dependence Of Operating Frequency On Filter Order |
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| 37. |
Design Of A Cmos System-On-Chip For Passive, Near-Field Ultrasonic Energy Harvesting And Back-Telemetry |
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| 38. |
Design Of A Network Of Digital Sensor Macros For Extracting Power Supply Noise Profile In Socs |
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| 39. |
Design Of Modified Second-Order Frequency Transformations Based Variable Digital |
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| 40. |
Filters With Large Cutoff Frequency Range And Improved Transition Band Characteristics |
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| 41. |
Design Of Silicon Photonic Interconnect Ics In 65-Nm Cmos Technology |
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| 42. |
Designing Tunable Subthreshold Logic Circuits Using Adaptive Feedback Equalization |
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| 43. |
Dual-Calibration Technique For Improving Static Linearity Of Thermometer Dacs For Io |
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| 44. |
Efficiency Enablers Of Lightweight Sdr For Mimo Baseband Processing |
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| 45. |
Efficient Dynamic Virtual Channel Organization And Architecture For Noc Systems |
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| 46. |
Efficient Synchronization For Distributed Embedded Multiprocessors |
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| 47. |
Emdbam A Low-Power Dual Bit Associative Memory With Match Error And Mask Control |
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| 48. |
Energy-Efficient Floating-Point Mfcc Extraction Architecture For Speech Recognition Systems |
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| 49. |
Enhanced Wear-Rate Leveling For Pram Lifetime Improvement Considering Process Variation |
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| 50. |
Error Resilient And Energy Efficient Mrf Message-Passing-Based Stereo Matching |
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| 51. |
Exploiting Intracell Bit-Error Characteristics To Improve Min-Sum Ldpc Decoding For Mlc |
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| 52. |
Nand Flash-Based Storage In Mobile Device Exploiting Intracell Bit-Error Characteristics To Improve Min-Sum Ldp |
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| 53. |
Fault Tolerant Parallel Ffts Using Error Correction Codes And Parseval Checks |
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| 54. |
Fcuda-Noc A Scalable And Efficient Network-On-Chip Implementation For The Cuda-To-Fpga Flow |
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| 55. |
Fixed-Point Computing Element Design For Transcendental Functions And Primary Operations In Speech Processing |
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| 56. |
Flexible Dsp Accelerator Architecture Exploiting Carry-Save Arithmetic |
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| 57. |
Flexible Ecc Management For Low-Cost Transient Error Protection Of Last-Level Caches |
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| 58. |
Floating-Point Butterfly Architecture Based On Binary Signed-Digit Representation |
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| 59. |
Glitch Energy Reduction And Sfdr Enhancement Techniques For Low-Power Binary-Weighted Current-Steering Dac |
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| 60. |
Gpu-Accelerated Parallel Sparse Lu Factorization Method For Fast Circuit Analysis |
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| 61. |
Graph-Based Transistor Network Generation Method For Supergate Design |
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| 63. |
Hardware And Energy-Efficient Stochastic Lu Decomposition Scheme For Mimo Receivers |
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| 64. |
High-Performance Nb-Ldpc Decoder With Reduction Of Message Exchange |
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| 65. |
High-Performance Pipelined Architecture Of Elliptic Curve Scalar Multiplication Over Gf(2m) |
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| 66. |
High-Speed And Energy-Efficient Carry Skip Adder Operating Under A Wide Range Of Supply Voltage Levels |
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| 67. |
Hybrid Lutmultiplexer Fpga Logic Architectures |
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| 68. |
Implementing Minimum-Energy-Point Systems With Adaptive Logic |
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| 69. |
In-Field Test For Permanent Faults In Fifo Buffers Of Noc Routers |
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| 70. |
Incorporating Process Variations Into Sram Electro Migration Reliability Assessment Using Atomic Flux Divergence |
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| 71. |
Input-Based Dynamic Reconfiguration Of Approximate Arithmetic Units For Video Encoding |
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| 72. |
Integrated Floating-Gate Programming Environment For System-Level Ics |
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| 73. |
Knowledge-Based Neural Network Model For Fpga Logical Architecture Development |
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| 74. |
Low-Cost High-Performance Vlsi Architecture For Montgomery Modular Multiplication |
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| 75. |
Low-Power Ecg-Based Processor For Predicting Ventricular Arrhythmia |
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| 76. |
Low-Power Fpga Design Using Memoization-Based Approximate Computing |
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| 77. |
Low-Power Split-Radix Fft Processors Using Radix-2 Butterfly Units |
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| 78. |
Low-Power System For Detection Of Symptomatic Patterns In Audio Biological Signals |
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| 79. |
Low-Powercost Rns Comparison Via Partitioning The Dynamic Range |
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| 80. |
Lut Optimization For Distributed Arithmetic-Based Block Least Mean Square Adaptive Filter |
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| 81. |
Measuring Improvement When Using Hub Formats To Implement Floating-Point Systems Under Round-To-Nearest |
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| 82. |
Memory-Aware Loop Mapping On Coarse-Grained Reconfigurable Architectures |
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| 83. |
Nand Flash Memory With Multiple Page Sizes For High-Performance Storage Devices |
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| 84. |
Network-On-Chip For Turbo Decoders |
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| 85. |
On Efficient Retiming Of Fixed-Point Circuits |
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| 86. |
One-Cycle Correction Of Timing Errors In Pipelines With Standard Clocked Elements |
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| 87. |
Online Measurement Of Degradation Due To Bias Temperature Instability In Srams |
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| 88. |
Optimized Built-In Self-Repair For Multiple Memories |
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| 89. |
Peva A Page Endurance Variance Aware Strategy For The Lifetime Extension Of Nand Flash |
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| 90. |
Power Efficient Level Shifter For 16 Nm Finfet Near Threshold Circuits |
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| 91. |
Proceed A Pareto Optimization-Based Circuit-Level Evaluator For Emerging Devices |
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| 92. |
Process Variation Delay And Congestion Aware Routing Algorithm For Asynchronous Noc Design |
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| 93. |
Read Bitline Sensing And Fast Local Write-Back Techniques In Hierarchical Bitline Architecture For Ultralow-Voltage Srams |
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| 94. |
Rf Power Gating A Low-Power Technique For Adaptive Radios |
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| 95. |
Source Code Error Detection In High-Level Synthesis Functional Verification |
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| 96. |
Source Coding And Pre-Emphasis For Double-Edged Pulse Width Modulation Serial Communication |
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| 97. |
Test Escapes Of Stuck-Open Faults Caused By Parasitic Capacitances And Leakage Currents |
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| 98. |
The Vlsi Architecture Of A Highly Efficient Deblocking Filter For Hevc Systems |
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| 99. |
Toward Solving Multichannel Rf-Soc Integration Issues Through Digital Fractional Division |
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| 100. |
Ultralow-Energy Variation-Aware Design Adder Architecture Study |
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| 101. |
Understanding The Relation Between The Performance And Reliability Of Nand Flashscm Hybrid Solid-State Drive |
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| 102. |
Unequal-Error-Protection Error Correction Codes For The Embedded Memories In Digital Signal Processors |
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