by nexgentech | Oct 24, 2017 | ieee project
A 2.4–3.6-GHz Wideband Sub-harmonically Injection-Locked PLL with Adaptive Injection Timing Alignment Technique Abstract: This paper proposes a wideband subharmonically injection-locked PLL (SILPLL) with adaptive injection timing alignment technique. The SILPLL...
by nexgentech | Oct 24, 2017 | ieee project
An All-MOSFET Sub-1-V Voltage Reference With a−51-dB PSR up to 60 MHz Abstract: This paper presents a voltage reference (VR) with a power supply rejection (PSR) better than 50 dB for frequencies of up to 60 MHz, and uses MOSFETs in strong inversion. Another innovation...
by nexgentech | Oct 24, 2017 | ieee project
Energy-Efficient VLSI Realization of Binary64 Division with Redundant Number Systems Abstract: VLSI realizations of digit-recurrence binary division usually use redundant representation of partial remainders and quotient digits. The former allows for fast carry-free...
by nexgentech | Oct 24, 2017 | ieee project
A 92-dB DR, 24.3-mW, 1.25-MHz BW Sigma–Delta Modulator Using Dynamically Biased Op Amp Sharing Abstract: A 2–2 cascaded switched-capacitor sigma-delta modulator is presented for design of low-voltage, low-power, broadband analog-to-digital conversion. To reduce power...
by nexgentech | Oct 24, 2017 | ieee project
A 0.1–2-GHz Quadrature Correction Loop for Digital Multiphase Clock Generation Circuits in 130-nm CMOS Abstract: A 100-MHz–2-GHz closed-loop analog in-phase/quadrature correction circuit for digital clocks is presented. The proposed circuit consists of a phase-locked...
by nexgentech | Oct 24, 2017 | ieee project
A Single Channel Split ADC Structure for Digital Background Calibration in Pipelined ADCs Abstract: A digital background calibration technique based on the concept of split analog-to-digital converter (ADC) structure is proposed for pipelined ADCs to correct the gain...
