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A Method to Design Single Error Correction Codes with Fast Decoding for a Subset of Critical Bits

by nexgentech | Oct 23, 2017 | ieee project

A Method to Design Single Error Correction Codes with Fast Decoding for a Subset of Critical Bits Abstract: Single error correction (SEC) codes are widely used to protect data stored in memories and registers. In some applications, such as networking, a few control...

Energy-Efficient Reduce-and-Rank UsingInput-Adaptive Approximations

by nexgentech | Oct 23, 2017 | ieee project

Energy-Efficient Reduce-and-Rank UsingInput-Adaptive Approximations Abstract: Approximate computing is an emerging design paradigm that exploits the intrinsic ability of applications to produce acceptable outputs even when their computations are executed...

ENFIRE: A Spatio-Temporal Fine-GrainedReconfigurable Hardware

by nexgentech | Oct 23, 2017 | ieee project

ENFIRE: A Spatio-Temporal Fine-GrainedReconfigurable Hardware Abstract: Field programmable gate arrays (FPGAs) are well-established as fine-grained reconfigurable computing platforms. However, FPGAs demonstrate poor scalability in advanced technology nodes due to the...

RoBA Multiplier: A Rounding-Based ApproximateMultiplier for High-Speed yet Energy-EfficientDigital Signal Processing

by nexgentech | Oct 23, 2017 | ieee project

RoBA Multiplier: A Rounding-Based ApproximateMultiplier for High-Speed yet Energy-EfficientDigital Signal Processing Abstract: In this paper, we propose an approximate multiplier that is high speed yet energy efficient. The approach is to round the operands to the...

A Dual-Clock VLSI Design of H.265 SampleAdaptive Offset Estimation for8k Ultra-HD TV Encoding

by nexgentech | Oct 23, 2017 | ieee project

A Dual-Clock VLSI Design of H.265 SampleAdaptive Offset Estimation for8k Ultra-HD TV Encoding Abstract: Sample adaptive offset (SAO) is a newly introduced in-loop filtering component in H.265/High Efficiency Video Coding (HEVC). While SAO contributes to a notable...

VLSI Design of 64bit × 64bit High Performance Multiplier with Redundant Binary Encoding

by nexgentech | Oct 23, 2017 | ieee project

VLSI Design of 64bit × 64bit High Performance Multiplier with Redundant Binary Encoding Abstract: For multiplier dominated applications such as digital signal processing, wireless communications, and computer applications, high speed multiplier designs has always been...

Temporarily Fine-Grained Sleep Technique forNear- and Subthreshold Parallel Architectures

by nexgentech | Oct 23, 2017 | ieee project

Temporarily Fine-Grained Sleep Technique forNear- and Subthreshold Parallel Architectures Abstract: This paper presents a design approach forimproving energy-efficiency and throughput of parallel architectures in near- and subthreshold voltage circuits. The focusis to...

A CROSS TENANT ACCESS CONTROL (CTAC) MODEL FOR CLOUD COMPUTING: FORMAL SPECIFICATION AND VERIFICATION

by nexgentech | Oct 23, 2017 | ieee project

ABSTRACT Sharing of resources on the cloud can be achievedon a large scale since it is cost effective and location independent.Despite the hype surrounding cloud computing, organizations arestill reluctant to deploy their businesses in the cloud computingenvironment...

ShakeIn: Secure User Authentication of Smartphones with Habitual Single-handed Shakes

by nexgentech | Oct 11, 2017 | ieee project

IEEE ANDROID PROJECTS IN PONDICHERRY ShakeIn: Secure User Authentication of Smartphones with Habitual Single-handed Shakes ABSTRACT: Smartphones have been widely used with a vast array of sensitive and private information stored on these devices. To secure such...

A Lightweight Secure Data Sharing Scheme for Mobile Cloud Computing

by nexgentech | Oct 11, 2017 | ieee project

IEEE ANDROID PROJECTS IN CHENNAI A Lightweight Secure Data Sharing Scheme for Mobile Cloud Computing Abstract: With the popularity of cloud computing, mobile devices can store/retrieve personal data from anywhere at any time. Consequently, the data security problem in...
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