Zero-Ripple Input Current High Step-Up Boost-SEPIC DC-DC Converter with Reduced Switch Voltage Stress
Abstract–
This paper proposes a zero-ripple input current high step-up boost-SEPIC DC-DC converter with reduced switch voltage stress to overcome some drawbacks of the conventional cascaded boost-SEPIC DC-DC converter. In the proposed converter, the input current ripple is significantly removed by the auxiliary circuit at the boost stage and the voltage gain is more increased by using turn ratio of a coupled inductor. at SEPIC stage. Additional, the switch voltage stress is reduced due to the clamping circuit and the revers-recovery problem of the output diode is alleviated by the leakage inductor. Hence, the low voltage rating MOSFET which has low R ds(on) can be utilized as a main switch device. Therefore, total power efficiency is improved. The theoretical analysis of the proposed converter is verified on an output 200[V]-200[W] prototype
PROPOSED SYSTEM:
The proposed high-step up boost-SEPIC DC-DC converter and the equivalent circuit diagram of the proposed converter is shown in Fig. 2 and Fig.3. The proposed converter is based on a cascaded boost-SEPIC converter with a common shared switch. The boost stage is composed of the coupled inductor T switch S 1 , the diodes D 1 and D consists of an auxiliary winding N 2 , the capacitor C 4 s of T 1 1 1 , the main common and the ripple-free circuit which , an auxiliary inductor L s , and an auxiliary capacitor C of 1:n L s 1 (n 1 a . The coupled inductor T =N p1 /N s1 1 has a magnetizing inductor L ) and a leakage inductor of T . The SEPIC stage includes the inductor L switch S 1 , the capacitor C 1 and C the clamping circuit composed of C coupled inductor T turn ratio of 1:n capacitances of C 2 2 (n 1 2 1 1 m1 with a turn ratio is included in the auxiliary inductor , coupled inductor T , the output diode D 3 and D has a magnetizing inductor L 2 , C =N 2, p2 C /N 3, s2 ). L and C k o 3 o 2 , the common , the output capacitor C for low switch voltage stress. The m2 and a leakage inductor L is assumed to be much smaller than the L are large enough that their voltages are considered to be constant. Because the average inductor voltage should be zero at the steady-state according to the volt-second balance law, the voltages across the C should be equal to V C1 , V C2 , V C3 , and V o . 1 , C 2 , C 3 k o , and with a m2 . The , and C o
EXISTING SYSTEM:
As the simplest methods, the boost converter can be cascaded or stacked up on the other step-up converter. However, the cascade structure requires a lot of components as numerous as the count of the stages, which brings on low efficiency, complex circuit and high cost. Therefore, it is commonly integrated as a single- switch converter by sharing main switch in order to reduce component count and circuit complexity. However, the conduction loss and switching loss is increased because each stage of the inductor current flows in one common switch. Hence, the sort switching is needed to improve power efficiency. There are several high step- up stacked boost converters in. The stacked-up structure is generally that both DC-DC converters are connected up in parallel by coupled inductor to obtain high voltage gain. Since the output capacitor is connected in series, the voltage valance of the output capacitors should be considered. In order to improve power efficiency, the zero-voltage-switching (ZVS) stacked converter which based on isolated boost-half bridge converter was proposed. In this converter, the ZVS operation can be improve power efficiency but a high circulating current is needed to satisfy wide range ZVS operation and a control circuit is complex due to asynchronous switches. In another way, an inductor is replaced with a coupled inductor to utilizing the turn ratio. There are several high step-up converter using coupled inductor. However, the voltage clamping circuit should be needed due to a leakage inductance of the coupled inductor . To overcome this problem, the active clamping circuit of buck-boost type is proposed. This clamping circuit not only reduces the switch voltage stress but also provides ZVS operation. However, more active switch and additional control circuit is required.
CONCLUSIONS
A zero-ripple input current high step-up boost-SEPIC DC-DC converter with reduced switch voltage stress is introduce in this paper. The proposed converter is based on the conventional cascaded boost-SEPIC DC-DC converter with a single switch. By comparison with conventional convent, the input current ripple is significantly removed by the ripple-free circuit and the voltage gain is higher by using a coupled inductor. Therefore, the proposed converter is suitable for fuel cell or renewable energy system. Moreover, the revers-recovery problem of the output diode is alleviated by the leakage inductor and the low voltage rating MOSFET which has ow R ds(on) can be utilized as a main switch because the switch voltage stress is significantly reduced. Therefore, total power efficiency is improved.
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