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An FPGA-Based Hardware Accelerator for Traffic Sign Detection

by nexgentech | Oct 24, 2017 | ieee project

An FPGA-Based Hardware Accelerator for Traffic Sign Detection Abstract: Traffic sign detection plays an important role in a number of practical applications, such as intelligent driver assistance and roadway inventory management. In order to process the large amount...

Reordering Tests for Efficient Fail Data Collection and Tester Time Reduction

by nexgentech | Oct 24, 2017 | ieee project

Reordering Tests for Efficient Fail Data Collection and Tester Time Reduction Abstract: During fail data collection, a tester collects information that is useful for defect diagnosis. If fail data collection can be terminated early, the tester time as well as the...

A Way-Filtering-Based Dynamic Logical–Associative Cache Architecture for Low-Energy Consumption

by nexgentech | Oct 24, 2017 | ieee project

A Way-Filtering-Based Dynamic Logical–Associative Cache Architecture for Low-Energy Consumption Abstract: Last-level caches (LLCs) help improve performance but suffer from energy overhead because of their large sizes. An effective solution to this problem is to...

Hardware-Efficient Built-In Redundancy Analysis for Memory with Various Spares

by nexgentech | Oct 24, 2017 | ieee project

Hardware-Efficient Built-In Redundancy Analysis for Memory with Various Spares Abstract: Memory capacity continues to increase, and many semiconductor manufacturing companies are trying to stack memory dice for larger memory capacities. Therefore, built-in redundancy...

Resource-Efficient SRAM-based Ternary Content Addressable Memory

by nexgentech | Oct 24, 2017 | ieee project

Resource-Efficient SRAM-based Ternary Content Addressable Memory Abstract: Static random access memory (SRAM)-based ternary content addressable memory (TCAM) offers TCAM functionality by emulating it with SRAM. However, this emulation suffers from reduced memory...

On Micro-architectural Mechanisms for Cache Wear out Reduction

by nexgentech | Oct 24, 2017 | ieee project

On Micro-architectural Mechanisms for Cache Wear out Reduction Abstract: Hot carrier injection (HCI) and bias temperature instability (BTI) are two of the main deleterious effects that increase a transistor’s threshold voltage over the lifetime of a microprocessor....
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