A Subthreshold Voltage Reference with Scalable Output Voltage for Low-Power IoT Systems
Abstract:
This paper presents a subthreshold voltage reference in which the output voltage is scalable depending on the number of stacked PMOS transistors. A key advantage is that its output voltage can be higher than that obtained with conventional low-power subthreshold voltage references. The proposed reference uses native NMOS transistors as a current source and develops a reference voltage by stacking one or more PMOS transistors. The temperature coefficient of the reference voltage is compensated by setting the size ratio of the native NMOS and stacked pMOS transistors to cancel temperature dependence of transistor threshold voltage and thermal voltage. Also, the transistor size is determined considering the trade-off between diode current between n-well and p-sub and process variation. Prototype chips are fabricated in a 0.18-μm CMOS process. Measurement results from three wafers show 3σ inaccuracy of ±1.0% from 0 °C to 100 °C after a single room-temperature trim. The proposed voltage reference achieves a line sensitivity of 0.31%/V and a power supply rejection of −41 dB while consuming 35 pW from 1.4 V at room temperature.
Existing System:
In contrast, subthreshold voltage references have lower power consumption (2.6 nW , 2.2 pW). The picowatt power consumption is achieved using the difference of two transistor threshold voltages (Vth). However, their output voltages can be quite low (e.g., ∼0.2 V). If this low voltage sets the operating voltage of analog blocks, it can significantly limit their dynamic range compared with the supply voltage (e.g., 3.8 V for a lithium battery operating system). A higher reference voltage (VREF) can be obtained with an analog voltage multiplier using an amplifier and resistors, but they can dwarf the power of the voltage reference itself. Thus, a new low-power voltage reference with a high VREF is desirable for battery-operated systems.
Proposed System:
This paper proposes a subthreshold voltage reference in which VREF is similar to that of bandgap voltage references (∼1.2 V). This higher VREF than in conventional subthreshold voltage references is the result of stacking four PMOS transistors and can be raised further by increasing the number of stacked transistors. We discuss the proposed voltage reference [18] in detail in this paper, including measurement results obtained using a newly fabricated design across multiple wafers. The prototype voltage reference is implemented in a standard 0.18-μm CMOS process, and measurement results show 3σ inaccuracy of ±1.0% from 0 °C to 100 °C after a single temperature trim while consuming 35 pW from a 1.4 V supply at room temperature. The proposed subthreshold voltage
reference shows limited noise performance (24.4 μV from 0.1 to 10 Hz) compared with conventional bandgap voltage references (6.1 μV [4] and 9.1 μV [7] from 0.1 to 10 Hz). Hence, such low-noise but high-power references might still be required to perform noise-critical operations. However, the proposed circuit can continually run and support other operations with less strict noise requirements without increasing the total system power significantly in low-power IoT systems.
Conclusion:
This paper proposes a subthreshold voltage reference with stacked pMOS transistors. The stacked transistors elevate the output voltage and help increase the dynamic range of analog circuits in battery-operated systems. The prototype voltage reference with four stacked pMOS transistors is fabricated in a standard 0.18-μm CMOS process. The measurement results from three different wafers show 3σ inaccuracy of ±1.0% from 0 °C to 100 °C with a single room-temperature trim with 35-pW power consumption at a 1.4 V supply and room
temperature.
References:
[1] Y. P. Chen, M. Fojtik, D. Blaauw, and D. Sylvester, “A 2.98nW bandgap voltage reference using a self-tuning low leakage sample and hold,” in IEEE Symp. VLSI Circuits Dig., Jun. 2012, pp. 200–201.
[2] J. M. Lee et al., “A 29nW bandgap reference circuit,” in IEEE Int. Solid- State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2015, pp. 100–101.
[3] A. Shrivastava, K. Craig, N. E. Roberts, D. D. Wentzloff, and B. H. Calhoun, “A 32nW bandgap reference voltage operational from 0.5V supply for ultra-low power systems,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2015, pp. 94–95.
[4] G. Ge, C. Zhang, G. Hoogzaad, and K. A. A. Makinwa, “A single-trim CMOS bandgap reference with a 3σ inaccuracy of ±0.15% from −40°C to 125°C,” IEEE J. Solid-State Circuits, vol. 46, no. 11, pp. 2693–2701, Nov. 2011.
[5] Y. Osaki, T. Hirose, N. Kuroki, and M. Numa, “1.2-V supply, 100-nW, 1.09-V bandgap and 0.7-V supply, 52.5-nW, 0.55-V subbandgap reference circuits for nanowatt CMOS LSIs,” IEEE J. Solid-State Circuits, vol. 48, no. 6, pp. 1530–1538, Jun. 2013.
[6] V. Ivanov, R. Brederlow, and J. Gerber, “An ultra low power bandgap operational at supply from 0.75 V,” IEEE J. Solid-State Circuits, vol. 47, no. 7, pp. 1515–1523, Jul. 2012.
[7] R. T. Perry, S. H. Lewis, A. P. Brokaw, and T. R. Viswanathan, “A 1.4 V supply CMOS fractional bandgap reference,” IEEE J. Solid-State Circuits, vol. 42, no. 10, pp. 2180–2186, Oct. 2007.
[8] Y.-S. Kuo et al., “MBus: A 17.5 pJ/bit/chip portable interconnect bus for millimeter-scale sensor systems with 8 nW standby power,” in Proc.IEEE Custom Integr. Circuits Conf., Sep. 2014, pp. 1–4.
[9] L. Magnelli, F. Crupi, P. Corsonello, C. Pace, and G. Iannaccone, “A 2.6 nW, 0.45 V temperature-compensated subthreshold CMOS voltage reference,” IEEE J. Solid-State Circuits, vol. 46, no. 2, pp. 465–473, Feb. 2011.
[10] B.-D. Yang, “250-mV supply subthreshold CMOS voltage reference using a low-voltage comparator and a charge-pump circuit,” IEEE Trans. Circuits Syst. II, Express Briefs, vol. 61, no. 11, pp. 850–854, Nov. 2014.