Publicly Verifiable Watermarking for Intellectual Property Protection in FPGA Design
Abstract:
Watermarking as a novel intellectual property (IP) protection technique can protect field-programmable gate array IPs from infringement. However, existing watermarking techniques may give away sensitive information during the public verification, which enables malicious verifiers or third parties to remove the embedded watermark and resell the design. Current zero-knowledge watermarking verification schemes can address the sensitive information leakage issue but are vulnerable to embedding attacks, which makes them ineffective in preventing the infringement denying of untrusted buyers (verifiers). This paper proposes a new publicly verifiable watermarking detection technique based on chaos-based zero-knowledge interaction and time stamping to resiliently resist the sensitive information leakage and embedding attacks, and is thus robust to the cheating from the prover, verifier, or third party. Experimental results and analysis show that the proposed method has better robustness than the most recent related literature The proposed architecture of this paper analysis the logic size, area and power consumption using Xilinx 14.2.
Existing System:
Current FPGA IP protection techniques can be roughly classed into two categories, active and passive. Active techniques devote to binding IPs on specific FPGA platforms to prevent infringement. Passive techniques mainly include bitstream encryption schemes and digital signature schemes. The bitstream encryption technique is to encrypt the configuration bitstream and then load it into an FPGA. For SRAM FPGAs, an FPGA design is stored in an external memory in the form of bitstream. Once the FPGA is started, the bitstream is loaded to configure the FPGA. In the configuration process, cloning the bitstream through the wiretap is possible [16]. Digital signature-based scheme is to embed an encrypted signature (e.g., watermark or fingerprint). into an IP to represent the ownership. When the IP is suspected of infringement, the IP owner can apply for a trusted third party (TTP) to recover the signature from the IP to prove the ownership. Digital signature is a novel technique applied to protect IP and has been widely studied for more than ten years.
In order to detect IP infringement, it will not be sufficient to focus on embedding the robust watermarks into IPs and detect the embedded watermarks effectively. Existing FPGA digital signature schemes verify marks by a designated verification team. However, it is difficult to ensure that all the members of the verification team are trusted in the real verification process. Therefore, the verification result announced by such a verification team may not be convincing to the IP buyer or IP owner. Correspondingly, for the public verification without the specified verification team involved, if the verifier can trace the marks embedded in IP, the verification result would be credible. However, in the public verification process, the prover will provide the sensitive information such as the content and embedded positions of marks to the verifier. Once the sensitive information is given away, malicious attackers can remove marks from the IP and then resell it. This is a serious threat to FPGA IP signature techniques. Furthermore, the FPGA IP is essentially a bitstream file. The embedded watermark or fingerprint in this file could be tampered with and covered more easily compared with ASIC. Public verification is a huge challenge in the field of FPGA IP watermarking, it is also one of the main obstacles to its application.
Disadvantages:
- Security is low
- Empirical values is high
Proposed System:
a new publicly verifiable watermarking detection scheme based on chaotic sequences is proposed to address the issues that the FPGA watermarking technique may leak the sensitive information and the existing zero knowledge FPGA watermarking detection scheme is vulnerable to embedding attacks. This scheme comprises the following.
1) The watermark is hidden in the unused lookup table (LUT) of used Slice, and the watermarking content of LUT of ˆ I is encrypted to prevent the leakage of watermarking content.
2) Since chaotic sequences have high randomness and low cross correlation, we can generate a real number chaotic sequence in each round of verification. The chaotic sequence is binarized into ρ, which is used as an input to the position mapping algorithm π(ρ)to control the location permutation of LUTs in FPGA bitstream, i.e., π(ρ)is applied to ˆ I to get the scrambled design ξ. Thenρand the position of the watermark inξ are used to interact between the prover and verifier. With the zeroknowledge protocol, the prover makes the verifier believe the watermark existing in IP without leaking the position information.
3) Timestamp is introduced to resist embedding attack to prevent dishonest IP buyers from denying.
Publicly verifiable water marking scheme:
Watermarking Generation and Embedding:
The process of watermarking generation and embedding are as follows.
Step 1: Watermarking generation. First, the signature S is encrypted with an encryption algorithm. Second, the encrypted Sis imputed into a one-way Hash function (such as SHA-2) to generate an abstractˆ S with fixed length. Finally, the watermark W is obtained by scrambling ˆ S with hashed chaotic sequence (the initial value of the chaos is used as the key K1).
Step 2: Locating watermark positions. Using a pseudorandom number generator (such as chaosK2as the key) to generate a pseudorandom sequence as the watermark embedding positions.
Step 3: Watermark embedding. The watermark is grouped according to the maximum value of the watermark in an LUT and then embedded into unused LUT of used Slice.
Step 4: The input and output of watermarked ILUTs are connected with the “do not care” inputs of the original circuit in order to disguise the embedded watermark.
Chaos-Based Zero-Knowledge Verification Protocol:
1) Protocol Overview: Zero-knowledge public verification is to prove that the watermark of IP owner exists in the bit stream of FPGA design without revealing the watermarking content and position. Assume the prover is Alice and the verifier is Bob. According to the watermark generation and embedding algorithm mentioned in Section III-A, Alice gets W based on S. Then W is embedded into I (FPGA design) to get ˆI. Alice wants to prove the existence of W without leaking its position. The process of zero-knowledge verification protocol is shown in Fig. 1. The steps of zero-knowledge watermarking verification protocol are as follows.
Figure 1: Zero-knowledge verification protocol between prover Alice andverifier Bob
2) Protocol Implementation: In the zero-knowledge watermarking detection protocol, the random permutation of the FPGA bitstream is an important component of the zero-knowledge protocol. Random permutation must meet two requirements: 1) the number of random permutations should be enough and 2) the correlation between random permutations should be extremely low. Chaotic phenomenon is the deterministic and random process that appears in nonlinear dynamic systems. The process is neither periodic nor convergent. The chaotic system is sensitive to the initial value and easy to produce a large number of pseudorandom number sequences whose cross correlation is extremely low. The chaotic sequence has good statistical properties [21]. Since the characteristics of chaotic sequences can exactly meet the special requirements of the random permutation of bitstream, this paper proposes to use chaotic mirror-like image encryption algorithm [22] to randomly permute the watermarking positions of bitstream. The random permutation algorithm is used to generate two-value chaotic sequences first. Then the two-value chaotic sequences are used as inputs of position mapping algorithm π(ρ)to control the LUT position permutation,π(ρ)is applied to ˆ I to get ξ.
Advantages:
- Security is high
- Empirical values is low
Software implementation:
- Modelsim
- Xilinx ISE