A Single Channel Split ADC Structure for Digital Background Calibration in Pipelined ADCs
Abstract:
A digital background calibration technique based on the concept of split analog-to-digital converter (ADC) structure is proposed for pipelined ADCs to correct the gain error induced by the capacitors mismatch and finite dc gain of the residue amplifiers and nonlinearity of the residue amplifiers. In the proposed technique, one of the channels in split ADC structure is virtually implemented by using two extra comparators in each ADC’s stage and an interpolation filter to eliminate the mismatch between channels. Several circuit-level simulation results in the context of a 12-bit 100-MS/s pipelined ADC are provided to verify the usefulness of the proposed calibration technique. The simulation results show 51-dB signal-to-noise and distortion ratio and 65-dB spurious free dynamic range improvement, respectively, in comparison with the noncalibrated ADC. The proposed architecture of this paper analysis the logic size, area and power consumption using Tanner tool.
Existing System:
Several digital calibration methods have been presented in the literature. The correlation of the ADC’s digital output with a pseudorandom sequence, which acts like an offset in the ADC, is calculated to correct the gain error and nonlinearity of the amplifier. The histogram of the ADC around the decision points of the sub-ADC is investigated to address the gain error. The main problem of the pseudorandom and histogram-based methods is that they require a long time to converge or lots of digital processing. To avoid these problems, equalization-based techniques have been presented in the literature. A slow but accurate ADC is used to calibrate the pipelined ADC and a reference digital-to-analog converter (DAC) along with the least mean square (LMS) algorithm is utilized. Equalization-based techniques benefit from the fast convergence time unlike the pseudorandom-based schemes. However, they need an accurate reference resulting in the analog design complexity and more power consumption. A semiequalization-based technique is used to reduce the convergence time of split ADC structures. Regarding this method, an unknown gain is added in the path of input signal to make a replica path for the pipelined ADC. This replica path and an interpolation filter are used to extract the gain error and nonlinearity of the amplifier. However, this increases the analog design complexity and also the calibration coefficients.
Figure 1: Circuit implementation of a 1.5-bit stage
Figure 2: Effect of circuit non-idealities in the (a) MDAC transfer function
A circuit implementation of commonly used 1.5-bit stage is shown in Fig. 1. This scheme offers the same gain property for the input signal and the DAC path. Hence, the capacitor mismatch and the amplifier gain error can be considered at the same way. In the rest of this brief, all signal voltages are normalized by Vref for simplicity. Fig. 2(a) shows the stage transfer function that has two discontinuities at the decision points,±0.25. Due to the circuit non idealities, the transfer function deviates from the ideal case and some missing codes appear at the ADC output around the decision points. Fig. 2(b) shows the ADC transfer function with a non-ideal first stage and an ideal backend ADC. Owing to the circuit non idealities in the first stage, some missing codes appear around±0.25.
Figure 3: Stage and its digital calibration model
The first stage and its digital domain calibration model are shown in Fig. 3. It should be mentioned that the ADC calibration starts from the last stage and ends in the first stage. Therefore, in the calibration of ith stage, the latter stages have been calibrated already and they are used as an ideal backend ADC to produce the digital equivalent of this stage’s output, Dres.
Disadvantages:
- Power consumption is high
- Area coverage is high
Proposed System:
a calibration technique based on the split ADC structure is proposed by using a single ADC and some extra comparators with an interpolation filter as the virtual ADC.
Split ADC-Based Calibration Technique:
In the split ADC structure, two same-pipelined ADCs work simultaneously. The final digital output is achieved by averaging the digital output of two channels. Besides, their subtraction can be used in the calibration process.
The method shifts the decision points of ADC in one of the channels, called channel A, in comparison with their counterparts in channel B. Thus, the transfer functions shown in Fig. 4 are produced. The channel Buses the original decision points of a 1.5-bit sub-ADC, i.e., ±0.25, while the other channel uses−0.125 and 0.375 decision points. With these two transfer functions, five different regions are created. In the regions i, iii ,and v, these two transfer functions are the same. Whereas, the regions ii and iv are the ones that can be used to extract the calibration coefficients with the LMS algorithm as follows:
Where e(n)=Dout,A−Dout,Bandμ1andμ3are the update step sizes of the first- and third-order coefficients, respectively. Moreover, Dres, A and Dres, B denote the digital outputs of backend ADCs for the stage under the calibration in channels A and B, respectively.
Figure 4: Stage’s transfer function of channels A and Bin the split structure
Proposed Calibration Technique:
In order to perform the digital background calibration, the structure of the proposed pipelined ADC has been improved to implement a single channel split ADC. As depicted in Fig. 5, two extra comparators along with an interpolation filter are utilized to implement the dual-mode transfer function of the split pipelined ADC.
Here, unlike the conventional structure, the stage decision points are placed at−0.375 and 0.125, respectively. Two extra comparators with decision point’s at−0.125 and 0.375 are added to the stage in order to perform the dual-mode transfer function. The main transfer curve relates to decision points of −0.375 and 0.125, while the auxiliary transfer curve is related to−0.125 and 0.375.
In the proposed calibration scheme, the difference between the main and auxiliary transfer curves in calibration regions,−0.375< Vin <−0.125 and 0.125 <Vin <0.375, are used to estimate the calibration coefficients. This choice for decision points results in twice wider calibration regions in comparison Thus, the convergence time of the proposed calibration technique is decreased. The main drawback of this choice is the limited offset voltage tolerance in the comparators.
Figure 5: Structure of the proposed calibration technique
The main transfer curve is considered for the normal operation of the pipelined ADC, while the auxiliary transfer curve is used in the calibration process. The single channel split ADC structure for the calibration is shown in Fig. 5. When the stage input sample is located in one of the calibration regions, a calibration cycle is done. In each calibration cycle, the stage is configured with the auxiliary transfer curve, while the main transfer curve is estimated with a 2Ltaps finiteimpulse response (FIR) interpolator. Indeed, the interpolator and two extra comparators act like a virtual ADC to implement the proposed single channel split pipelined ADC.
Figure 6: Timing diagram of the proposed calibration scheme
The proposed calibration technique is performed adaptively and updates the coefficients at each calibration cycle, which consists of N input samples. Timing diagram of the calibration process is shown in Fig. 6. In each calibration cycle, the ADC produces one sample based on the auxiliary transfer curve, i.e., the desired sample in Fig. 6. When the desired sample is located in the one of calibration regions.
Advantages:
- Low power consumption
- Area coverage is low
Software implementation:
- Tanner tool